Wafer Security Mask Shift Encoding for Tamper Detection
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Solution Overview
Problem
In the manufacturing of complex integrated circuits, existing verification processes are inadequate to detect malicious features introduced during fabrication, leading to potential tampering and counterfeiting of chips and wafers, as conventional ID methods are not secure and may not be detectable until late in the production process, resulting in wasted resources and compromised product quality.
Innovation Solution
Incorporating a security mask with predetermined shifts into the integrated circuit or wafer, which encodes an identifier that can be verified using conventional metrology, allowing for secure design verification and inspection throughout the fabrication workflow, thereby preventing tampering and counterfeiting by encoding information that is detectable through inline metrology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ID methods are used for wafer and chip identification, then the manufacturing process remains simple, but the security against tampering and counterfeiting is insufficient
Solution Approach 1:
The patent merges the identification function with the existing product mask structure by overlaying a security mask with predetermined shifts. This combines the product identification and security verification functions into a single integrated structure, eliminating the need for separate ID tags or markers while providing secure tamper detection capability
Solution Approach 2:
The patent creates a copy of the product mask pattern (the security mask) that is deliberately shifted by predetermined amounts. This copied pattern serves as an authentication reference that can be verified through metrology without adding functional complexity to the actual circuit operation
2Reliability
If verification is performed only at late stages of production, then the manufacturing process remains efficient, but resources are wasted when tampering is detected
Solution Approach 1:
The security mask is incorporated into the wafer during the fabrication process itself, enabling verification to be performed at any stage from manufacturing through distribution. This preliminary integration of the security feature allows continuous verification capability, preventing resource waste by detecting tampering early rather than only at late production stages
3Reliability
If a security mask with predetermined shifts is incorporated into the wafer, then secure identification and verification throughout the fabrication process becomes possible, but the manufacturing process complexity increases
Solution Approach 1:
The security mask is merged with the product mask as a single integrated structure rather than separate components. The security mask uses the same lithography process and materials as the product mask, combining two functions into one physical structure that does not add separate manufacturing steps or complex additional components
Data Source
AI summary
Embodiments are disclosed for a method. The method includes generating a correction datastore indicating shifts in magnitude representing corresponding characters that uniquely identify hardware comprising a computer processing chip. The method further includes generating security masks based on a correction file. Additionally, the method includes using a correction process for the computer processing chip. The generated security masks include corresponding overlays representing the shifts in magnitude with respect to corresponding product masks for the computer processing chip. The method also includes generating the computer processing chip using the security masks and the product masks.