Wafer Segmentation for Semiconductor Packaging Yield

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Solution Overview

Problem

High failure rates in semiconductor wafers due to manufacturing defects lead to wasted manufacturing capacity and increased costs when whole wafers with excessive failed regions are processed for packaging, reducing the yield of finished products.

Innovation Solution

A semiconductor device packaging method involving wafer pieces with active and back surfaces, bonded to a carrier substrate using an adhesive layer, with through silicon vias and redistribution circuit layers for electrical connection, followed by packaging layer filling and sawing to create individual packaging structures, thereby reducing processing costs and improving yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If whole wafers are processed for packaging despite manufacturing defects, then manufacturing capacity is utilized, but yield of finished products decreases and manufacturing cost increases

Engineering Contradiction:
Improvemanufacturing capacity utilizationVSAvoidyield of finished products
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides a whole wafer into multiple wafer pieces, each containing one or more semiconductor devices. This segmentation allows selective processing of only the functional portions of the wafer, separating good regions from defective regions. By processing wafer pieces instead of entire wafers, the method utilizes manufacturing capacity effectively while avoiding inclusion of defective devices, thus maintaining high yield.

Inventive Principle:
Principle #1Segmentation

2Productivity

If whole wafers are processed for packaging, then manufacturing capacity is utilized, but manufacturing cost increases

Engineering Contradiction:
Improvemanufacturing capacity utilizationVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSLoss of substance

Solution Approach 1:

The patent segments wafers into wafer pieces based on functional regions, allowing processing of only necessary portions. This reduces waste of manufacturing resources on defective areas while maintaining capacity utilization, thereby lowering overall manufacturing cost per good device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different processing treatments to different regions of the wafer. Functional regions undergo packaging processing while defective regions are excluded. This local quality approach ensures resources are allocated only to viable devices, reducing waste and lowering manufacturing costs.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method allows for efficient packaging of only available wafer regions, reducing costs and enhancing semiconductor device yield by utilizing current equipment and preventing damage from water vapor and external forces.

Implementation Method 1

an adhesive layer is formed on the carrier substrate, and then the packaging region of each of the wafer pieces is bonded to the adhesive layer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS9070672B2Semiconductor device packaging structure and packaging method
Publication Date: 2015.06.30 XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
  • US9070672B2 patent drawing
  • US9070672B2 patent drawing
  • US9070672B2 patent drawing

AI summary

Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.