Semiconductor Wafer Separation Zone for Narrower Plasma Dicing
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Solution Overview
Problem
The increasing demand for smaller, high-speed semiconductor devices has led to challenges in maintaining yield and throughput due to the complexity and time required for dicing semiconductor wafers into smaller chips, as the number of chips per wafer increases, necessitating a more efficient separation mechanism.
Innovation Solution
A semiconductor wafer design featuring a separation zone with a scribe line configured for plasma etching, utilizing plasma etch-resistant material layers and a passivation layer to define an inlet area, which reduces the width of the separation zone and enhances the dicing process efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of chips per wafer is increased to meet demand, then productivity improves, but the dicing time and process complexity increase
Solution Approach 1:
The separation zone is divided into multiple distinct layers including plasma etch-resistant material layers, passivation layers, and seal rings. This segmentation allows each layer to perform its specific function efficiently, enabling faster and more reliable dicing operations as the number of chips per wafer increases
Solution Approach 2:
The plasma etch-resistant material layers and passivation layers are pre-configured during wafer fabrication to define the separation zone boundaries before dicing begins. This preliminary structuring eliminates the need for complex real-time dicing decisions, reducing dicing time while maintaining high chip density
2Productivity
If the number of chips per wafer is increased to meet demand, then productivity improves, but the dicing process complexity increases
Solution Approach 1:
Different materials with specific properties are used in different zones of the separation structure. The plasma etch-resistant material layers provide resistance where needed, while passivation layers provide sealing in other areas. This localized optimization simplifies the overall dicing process by making each zone's function predictable and manageable
Solution Approach 2:
The plasma etch-resistant material layers act as intermediary structures between the chips and the dicing process. These layers facilitate the separation process by providing clear etching boundaries and protecting adjacent chips, thereby reducing process complexity despite high chip density
3Area of moving object
If the separation zone width is reduced to increase chip density, then chip density improves, but the separation efficiency may deteriorate
Solution Approach 1:
The separation zone employs a composite structure with multiple material layers including plasma etch-resistant materials and passivation materials. This composite approach allows the separation zone to maintain sufficient functional width for efficient dicing while minimizing the overall space occupied, thereby preserving both chip density and separation efficiency
Solution Approach 2:
Instead of increasing separation zone width in the horizontal plane to improve separation efficiency, the invention adds vertical dimensionality through multiple stacked layers. This allows the separation function to be achieved in the vertical dimension, freeing up horizontal space for higher chip density while maintaining separation efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design optimizes the dicing process by reducing the width of the separation zone and improving the separation efficiency of small semiconductor chips, thereby increasing chip density and reducing production costs while maintaining process complexity.
Implementation Method 1
a scribe line configured to be diced using plasma etching
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
The invention relates to a semiconductor wafer (1a, 1b) comprising a plurality of chips (2) and a separation zone (3) spacing the semiconductor chips (2) from each other in this wafer (1a, 1b), such a separation zone (3) extending from a front face (4a) to an opposite backside face (4b) of this wafer (1a, 1b), this separation zone (3) includes a scribe line (6) configured to be diced using plasma etching and an inlet area (13) of this scribe line (6), the inlet (13) being delimitated by free ends of plasma etch-resistant material layers (9) extending each from a peripheral wall (20) of a functional part (18) of a chip (2) into the scribe line (6) by overlapping a top of a seal ring (7) of this chip (2).