Wafer Sequence Generator for Defect Detection
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Solution Overview
Problem
In semiconductor wafer processing, randomizing the wafer processing order often results in chance correlations between sequences, making it difficult to identify faulty equipment or subsystems, as different processing steps appear correlated to a given yield excursion signature, thereby reducing the effectiveness of fault isolation analysis.
Innovation Solution
A method and system for sequencing wafer processing order to minimize sequence correlation in a cyclical two-pattern model by generating and indexing sequences of wafer identifiers, ensuring that each sequence matches the required number of wafer identifiers in every sequence previously indexed, thereby processing wafers in specific subsystems to reduce chance correlations and enhance defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wafer processing order is randomized to improve fault isolation analysis, then defect detection capability is improved, but sequence correlations between processing steps are created that reduce detection accuracy
Solution Approach 1:
The patent segments the wafer processing sequence into multiple independent subsequences, where each subsequence represents a distinct processing path through different equipment subsystems. By dividing the overall processing flow into separable segments, the system can analyze correlations within each segment independently, reducing spurious correlations between unrelated processing steps while maintaining detection sensitivity for actual defects.
2Difficulty of detecting and measuring
If wafer processing order is shuffled to identify faulty equipment, then fault isolation capability is improved, but chance correlations between processing steps are created that reduce analysis effectiveness
Solution Approach 1:
The patent performs preliminary actions by pre-processing the wafer sequence data to identify and remove obviously correlated segments before conducting fault isolation analysis. This preliminary processing step eliminates spurious correlations in advance, allowing subsequent analysis to focus on genuine fault patterns without being confounded by artificial sequence correlations.
Solution Approach 2:
The patent introduces an intermediary processing layer that acts as a mediator between the raw wafer sequence data and the fault isolation analysis. This intermediary layer includes algorithms that detect and correct spurious correlations, effectively filtering out noise before the data reaches the fault isolation stage, thereby preserving genuine fault information while eliminating false correlations.
Data Source
AI summary
A method of sequencing wafer processing order to minimize sequence correlation in a cyclical two pattern model by generating a set of sequences of wafer identifiers that each specify an order by which one or more fabrication equipments processes wafers of a wafer lot, where the wafer lot contains a number of slots and the fabrication equipments each includes a first subsystem for processing wafers in odd-numbered slots of the first wafer lot and a second subsystem for processing wafers in even-numbered slots of the first wafer lot, and where each of the generated wafer sequences contains exactly a number of wafer identifiers that match the wafer identifiers in every other wafer sequence indexed in the set.