Wafer Shape Metrology for Target-Free Post-Bond Overlay Prediction

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Solution Overview

Problem

Conventional methods for measuring post-bonding overlay between semiconductor wafers require metrology targets, which can complicate the bonding process and limit measurement density, especially when placed on carrier wafers.

Innovation Solution

A wafer metrology system that performs stress-free shape measurements on individual wafers and post-bonded pairs, using a controller to predict overlay between features based on shape data and provide feedback or feedforward adjustments to process tools, potentially eliminating the need for targets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If metrology targets are placed on carrier wafers to measure post-bonding overlay, then overlay measurement can be performed, but additional processing is required and measurement density is limited

Engineering Contradiction:
Improveoverlay measurementVSAvoidadditional processing
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the metrology targets from the carrier wafer and places them directly on the device wafer. This eliminates the need for additional processing to place targets on the carrier wafer, while still enabling overlay measurement through the carrier wafer using infrared light penetration.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses the device wafer itself as an intermediary to carry the metrology targets. The device wafer serves as both the functional substrate and the carrier for measurement targets, eliminating the need for a separate carrier wafer target placement process.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If metrology targets are placed on carrier wafers to measure post-bonding overlay, then overlay measurement can be performed, but measurement density is limited

Engineering Contradiction:
Improveoverlay measurementVSAvoidmeasurement density
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent extracts the metrology targets from the carrier wafer and places them directly on the device wafer. This enables multiple targets to be placed on the device wafer without being constrained by carrier wafer placement limitations, thereby increasing measurement density.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the placement dimension from carrier wafer surface to device wafer surface, allowing targets to be positioned in locations that would be inaccessible or impractical on the carrier wafer, thus increasing the number and density of measurable points.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If infrared light is used to penetrate silicon wafers for overlay measurement, then overlay can be measured through the wafer, but the method requires metrology targets on both wafers

Engineering Contradiction:
Improveoverlay measurement through waferVSAvoidtargets on both wafers
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the requirement for targets on both wafers and reduces it to targets on only the device wafer. By placing targets on the device wafer and using infrared light penetration through the carrier wafer, the system eliminates the need for targets on the carrier wafer.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The device wafer with its placed targets serves itself as the measurement reference. The infrared light penetrates the carrier wafer to detect these targets, making the device wafer both the object of measurement and the source of measurement references.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables accurate prediction and minimization of overlay errors in wafer bonding processes, improving measurement density and reducing additional processing requirements, thus enhancing the reliability of semiconductor fabrication.

Implementation Method 1

a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first wafer and the second wafer

Methodology Applied
Scientific EffectInterferometry: Interference

Data Source

PatentUS11829077B2System and method for determining post bonding overlay
Publication Date: 2023.11.28 KLA CORP
  • US11829077B2 patent drawing
  • US11829077B2 patent drawing
  • US11829077B2 patent drawing

AI summary

A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.