Wafer Singulation via Inverted Dicing and Imprinted Alignment
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Solution Overview
Problem
The existing methods for singulating semiconductor chips from a wafer often result in the formation of burrs and cracks, which negatively impact electrical performance and are difficult to align due to the invisibility of the chip pattern from the metal layer side, leading to potential damage during cutting.
Innovation Solution
A method involving partial dicing through the semiconductor substrate, where first trenches are cut on the active surface and imprinted on the metallization layer, allowing for accurate alignment and subsequent full-thickness dicing through the metallization layer, minimizing burrs and cracks, and enabling optical alignment for precise chip singulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sawing is performed from the metal layer side, then the cutting process can be completed, but burrs and cracks are generated and alignment is difficult due to invisibility of chip pattern
Solution Approach 1:
The patent inverts the conventional sawing approach by first performing partial dicing from the active surface (where chip pattern is visible) and then completing the cut from the metal layer side. This reversal allows alignment to be established when the pattern is visible, then transferred to guide the final cutting step.
Solution Approach 2:
The patent performs preliminary partial dicing from the active surface to create alignment marks and establish the cutting path before performing the final cut from the metal layer side. This preliminary action creates visible references that guide the subsequent cutting operation.
2Productivity
If sawing is performed from the metal layer side, then the cutting process can be completed, but burrs and cracks are generated affecting electrical performance
Solution Approach 1:
The patent performs preliminary partial dicing from the active surface to create a controlled initial cut that establishes the cutting path. This preliminary action prevents uncontrolled cracking and burr formation during the final cut from the metal layer side, as the material has already been partially separated along the intended path.
Solution Approach 2:
The patent segments the cutting process into two distinct stages: partial dicing from the active surface and completion from the metal layer side. This segmentation allows each stage to be optimized independently, with the first stage creating a controlled partial separation and the second stage completing the singulation with minimal damage.
3Ease of operation
If blind sawing is performed from metal layer side, then cutting can proceed without alignment, but chip damage is likely due to misalignment
Solution Approach 1:
The patent performs preliminary partial dicing from the active surface where the chip pattern is visible, creating alignment marks and establishing the cutting path. This preliminary action provides visual references that eliminate the need for blind alignment during the final cut from the metal layer side.
Solution Approach 2:
The partial dicing from the active surface creates a physical copy or imprint of the chip pattern on the metal layer side through the wafer thickness. This copied pattern serves as a template that guides the final cutting operation, ensuring accurate alignment without requiring direct visual observation during the final cut.
Data Source
AI summary
A method of making an integrated circuit includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first trench in the semiconductor wafer extending from one of the first surface and the second surface toward an other of the first surface and the second surface. The method further includes sawing a second trench in the other surface until the second trench communicates with the first trench, thus singulating the integrated circuit from the semiconductor wafer.