Wafer Singulation Passivation Layout for Faster Plasma Dicing

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Solution Overview

Problem

The etch rate of nitride-containing passivation layers in semiconductor devices is too low for efficient plasma dicing, requiring a thick mask layer for protection, which is not feasible due to high photoresist etch rates.

Innovation Solution

Removing the nitride-containing passivation layers from the dicing regions allows for faster plasma etching through the semiconductor device without the need for a thick mask layer, facilitating easier singulation of individual semiconductor dies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If nitride-containing passivation layers are used to protect interconnect structures, then device reliability is improved, but plasma dicing speed deteriorates due to low etch rate

Engineering Contradiction:
Improvedevice reliabilityVSAvoidplasma dicing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The passivation layer structure is segmented into multiple functional layers: a nitride-containing passivation layer for device protection and a sacrificial layer for enabling plasma dicing. This segmentation allows each layer to perform its specific function without compromising the other, resolving the contradiction between reliability and dicing speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The harmful effect of the nitride-containing passivation layer (low etch rate blocking plasma dicing) is extracted by introducing a separate sacrificial layer that is specifically designed to be etched away during plasma dicing. This removes the obstacle to fast dicing while preserving the protective passivation layer.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If a thick mask layer is applied to protect device regions during plasma dicing, then device protection is improved, but photoresist etch rate becomes insufficient to complete the process

Engineering Contradiction:
Improvedevice protectionVSAvoidphotoresist etch rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

A sacrificial layer acts as an intermediary between the device regions and the plasma dicing process. This layer provides the necessary protection during dicing (allowing standard-thickness photoresist to be used) while being easily removable, thus enabling both device protection and maintaining photoresist etch rate compatibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If photoresist thickness is increased to protect device regions during plasma dicing, then device protection is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedevice protectionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sacrificial layer functions as a disposable protective element that is applied temporarily during plasma dicing and then completely removed. This allows the use of standard-thickness photoresist (reducing complexity) while still providing necessary protection during the dicing process, as the sacrificial layer is discarded after serving its purpose.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables faster and more efficient plasma dicing, increasing manufacturing throughput and reducing production costs by eliminating the need for thick mask layers and improving die strength and reliability.

Implementation Method 1

plasma dicing

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS20250183192A1Passivation scheme design for wafer singulation
Publication Date: 2025.06.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250183192A1 patent drawing
  • US20250183192A1 patent drawing
  • US20250183192A1 patent drawing

AI summary

A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.