Wafer-Scale SiP Molding Structure for Warpage Control
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Solution Overview
Problem
The existing wafer-scale system-in-package structures face significant warpage issues due to unbalanced thermal expansion coefficients and Young's moduli between the upper and lower surfaces, leading to deformation and processing challenges, especially in large-scale chiplet modules.
Innovation Solution
A wafer-scale system-in-package structure is designed with a substrate having semiconductor chips flip-chipped on its upper surface, wrapped by a first molding layer, and external protrusions on its lower surface, which are further wrapped by a second molding layer with specific thermal expansion and Young's modulus properties to balance the thermal stresses, along with trimming of molding layer edges to reduce material proportion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a wafer-scale system-in-package structure is designed with large-size substrates to integrate multiple semiconductor chips, then the integration density and functionality are improved, but warpage control deteriorates due to unbalanced thermal expansion coefficients and Young's moduli between upper and lower surfaces
Solution Approach 1:
The patent applies asymmetry by designing different molding layer configurations for the upper and lower surfaces of the substrate. The first molding layer on the upper surface has different thickness and material properties compared to the second molding layer on the lower surface. This asymmetric structure compensates for the unbalanced thermal expansion coefficients and Young's moduli, effectively controlling warpage while maintaining high integration density on the wafer-scale substrate
Solution Approach 2:
The patent changes physical parameters of the molding layers, specifically adjusting the thickness, thermal expansion coefficient, and Young's modulus of the first and second molding layers. By optimizing these parameters differently for each surface, the structure achieves thermal stress balance, preventing warpage deformation in large-scale chiplet modules while preserving high integration capability
2Strength
If the thickness of molding layers is increased to provide better structural support and electrical insulation, then mechanical strength and electrical performance are improved, but thermal stress imbalance worsens, leading to increased warpage
Solution Approach 1:
The patent applies local quality by assigning different thickness and material properties to the first molding layer on the upper surface and the second molding layer on the lower surface. The upper molding layer is optimized for mechanical support and electrical insulation, while the lower molding layer is specifically designed with adjusted parameters to counterbalance thermal stresses, thereby preventing warpage without compromising overall structural strength
3Ease of manufacture
If uniform molding layers are applied on both upper and lower surfaces for simplicity, then manufacturing complexity is reduced, but thermal expansion imbalance causes severe warpage in large-scale structures
Solution Approach 1:
The patent deliberately introduces asymmetry in the molding layer design, where the first molding layer on the upper surface and the second molding layer on the lower surface have different thicknesses and material properties. This asymmetric configuration is specifically engineered to compensate for the inherent thermal expansion coefficient imbalance in wafer-scale substrates, effectively controlling warpage while remaining manufacturable through standard processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively controls warpage at room temperature or high temperature by balancing thermal expansion and Young's moduli, preventing deformation and ensuring stable processing of large-scale chiplet modules.
Implementation Method 1
at least one of the coefficient of thermal expansion or Young's modulus of the second molding layer is equal to or higher than that of the first molding layer
Data Source
AI summary
A wafer-scale system-in-package structure and a forming method thereof are disclosed. The package structure includes: a substrate, where the substrate includes an upper surface and a lower surface that are opposite to each other; a first molding layer that wraps the plurality of semiconductor chips and the upper surface of the substrate; external protrusions on the lower surface of the substrate; and a second molding layer that wraps side surfaces of the plurality of external protrusions and the lower surface of the substrate, where a thickness of the second molding layer is less than a thickness of the first molding layer, and at least one of the coefficient of thermal expansion or Young's modulus of the second molding layer is equal to or higher than that of the first molding layer. In this way, warpage of the system-in-package structure can be effectively controlled.