Wafer Slot Allocation Using Reinforcement Learning in Batch Tools

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Solution Overview

Problem

The challenge in semiconductor manufacturing processes using batch equipment is the occurrence of quality deviations and increased defect rates due to suboptimal wafer arrangements, which complicates the determination of an efficient slot allocation.

Innovation Solution

A method and apparatus utilizing reinforcement learning and optimization algorithms to optimize wafer-specific slot locations by training a model with characteristic and historical data, executing an optimization algorithm, and selecting a final algorithm based on system requirements to minimize defect rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If batch equipment is used to simultaneously process multiple wafers, then productivity and process efficiency are improved, but quality deviation and defect rate increase due to suboptimal wafer arrangement

Engineering Contradiction:
Improveprocess efficiencyVSAvoidquality deviation
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by assigning different slot positions to wafers based on their individual characteristics and process requirements. Each wafer receives a customized slot allocation within the batch equipment, ensuring that specific wafers are positioned in optimal locations to minimize quality deviation while maintaining overall batch processing efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of wafer arrangement by using reinforcement learning to dynamically determine optimal slot allocations. The system learns from historical data and adjusts slot positions based on wafer characteristics, process conditions, and quality requirements, transforming the fixed arrangement into an adaptive, optimized configuration.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If reinforcement learning model is trained with comprehensive wafer data, then slot allocation optimization accuracy is improved, but training time and computational complexity increase

Engineering Contradiction:
Improveoptimization accuracyVSAvoidtraining time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-training the reinforcement learning model with historical wafer data and slot allocation patterns before actual production use. This offline training phase allows the model to learn optimal allocation strategies in advance, so that during real-time batch processing, the model can quickly provide accurate slot recommendations without extensive computation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses partial action by selectively training the model on the most critical and representative features of wafer data rather than processing all possible parameters. This focused approach achieves sufficient optimization accuracy while significantly reducing training time and computational resources required.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20260037708A1Method and apparatus for optimizing slot allocation of wafers in batch equipment of semiconductor manufacturing process
Publication Date: 2026.02.05 SAMSUNG ELECTRONICS CO LTD
  • US20260037708A1 patent drawing
  • US20260037708A1 patent drawing
  • US20260037708A1 patent drawing

AI summary

A method of optimizing a slot allocation of a wafer in batch equipment of a semiconductor manufacturing process is provided. The method includes loading wafer-specific characteristic data and slot allocation history data, training a reinforcement learning model by using the wafer-specific characteristic data and the slot allocation history data, executing an optimization algorithm for determining a wafer-specific optimum slot location, based on the reinforcement learning model; based on a time for executing the optimization algorithm satisfying a system requirement time, selecting the optimization algorithm as a final algorithm, and allocating a wafer-specific slot in the batch equipment in a next process by using the final algorithm.