Wafer Sort Defect Detection via GDS Coordinate Correlation
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Solution Overview
Problem
Current wafer testing methods, such as Wafer Sort (WS), face challenges in accurately matching defects, calculating killing ratios, and identifying yield impact layers due to lack of site-specific data and difficulty in correlating defects with physical locations.
Innovation Solution
A method and system that utilize a WS testing apparatus to obtain DTL or ADART results, highlighting repaired sites, and matching them with graphic data system (GDS) design layout coordinates to generate defect-related data, including killing ratios and patterns of interest, using analysis equipment like E-beam inspection tools, to correlate repair sites with defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Wafer Sort testing is performed to test all integrated circuits on the wafer, then product yield is improved, but defect matching accuracy deteriorates due to lack of site-specific data
Solution Approach 1:
The patent segments the wafer testing process into two distinct phases: Wafer Sort testing for yield improvement, and subsequent defect inspection using E-beam or optical tools for precise defect matching. This segmentation allows each phase to optimize for its specific goal without compromise
Solution Approach 2:
The patent introduces an intermediary correlation process that maps Wafer Sort failure bins to physical defect locations using inspection tool data. This intermediary step bridges the gap between electrical test results and physical defect identification, enabling accurate defect matching despite the limitations of Wafer Sort alone
2Productivity
If Wafer Sort results are used to identify defects, then testing efficiency is improved, but defect location correlation deteriorates due to difficulty in matching with physical locations
Solution Approach 1:
The patent merges Wafer Sort electrical test data with physical inspection data from E-beam or optical inspection tools. By combining these two data sources through coordinate correlation and failure bin mapping, the system recovers the lost location information while maintaining testing efficiency
Solution Approach 2:
The patent replaces the mechanical/physical limitation of Wafer Sort (which cannot provide precise location data) with a data-driven correlation system using inspection tool images and coordinate systems. This substitution transforms the problem from a physical measurement limitation to a data processing solution
3Measurement precision
If additional testing recipes are implemented to improve defect detection accuracy, then defect detection capability is improved, but system complexity increases
Solution Approach 1:
The patent makes the existing inspection tools (E-beam or optical inspection tools) multi-functional by using them for both primary defect inspection and secondary correlation with Wafer Sort data. This universal usage eliminates the need for dedicated additional testing equipment while improving defect detection capability
Solution Approach 2:
The patent changes the operational parameters of existing inspection tools by configuring them to output data in specific formats that enable correlation with Wafer Sort failure bins. By adjusting data output parameters rather than adding equipment, the system improves defect detection without increasing complexity
Data Source
AI summary
A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.