Wafer Stack Corner Geometry for Chipping Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional wafer stacking techniques face challenges in thin-down processes, particularly due to chipping risks associated with the application of force during thickness reduction, as existing methods do not adequately address the geometry and bonding issues that increase the risk of edge chipping.
Innovation Solution
The solution involves designing wafers with specific rounded corner configurations and bonding techniques, such as fusion bonding or anodic bonding, where the second wafer has smaller rounded corners or right-angle corners to minimize the non-bonded area, thereby reducing the chipping risk during thin-down processes by decreasing the distance between the bonding layer and the edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer stacking techniques are used with standard corner configurations, then the wafer bonding process can be completed, but chipping risk increases during thin-down processes due to larger non-bonded areas at the edges
Solution Approach 1:
The patent applies local quality by differentiating the corner configurations between wafers. The first wafer has first corners with a first radius of curvature, while the second wafer has second corners with a second radius of curvature that is smaller than the first. This local differentiation at the corner regions reduces the non-bonded area and minimizes chipping risk during thin-down processes, while the rest of the wafer structure remains standard.
2Reliability
If the second wafer has smaller rounded corners to reduce non-bonded area, then chipping risk decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring the second wafer with smaller radius corners before the bonding process. This preliminary geometric optimization ensures that when the wafers are bonded and subjected to thin-down processes, the reduced non-bonded area at the edges inherently resists chipping. The corner geometry is established in advance to prevent rather than correct potential damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases the chipping risk of the second wafer by reducing the non-bonded area and the associated chipping risk, compared to conventional wafer stacks with standard corner configurations, leading to a more reliable and efficient thin-down process.
Implementation Method 1
bonding techniques, such as fusion bonding or anodic bonding
Implementation Method 2
bonding techniques, such as fusion bonding or anodic bonding
Data Source
AI summary
A semiconductor device includes a first wafer and a second wafer. The first wafer has a top portion. The second wafer is disposed on the top portion of the first wafer, wherein the second wafer has a bottom portion bonded on the top portion of the first wafer, and a non-bonded area of the bottom portion has a width smaller than 0.5 mm. The bottom portion of the second wafer has a size smaller than or equal to that of the top portion of the first wafer. In some embodiments, the top portion of the first wafer has first rounded corners, and the bottom portion of the second wafer has second corners. A cross-sectional view of each of the second rounded corners has a radius smaller than that of each of first rounded corners. In some embodiments, the bottom portion of the second wafer has right angle corners.