Wafer Stack Edge Trimming Guided by Acoustic Defect Inspection
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Solution Overview
Problem
Wafer stack structures often develop edge defects such as cracks and bubbles after bonding, which affect yield and need to be effectively removed.
Innovation Solution
A wafer stacking method involving edge defect inspections using a C-mode scanning acoustic microscope (CSAM) followed by trimming processes with widths greater than or equal to the measured defect distances, accompanied by thinning and passivation layers to prevent cross-contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafers are bonded together to form a wafer stack structure, then the three-dimensional integration is achieved, but edge defects (cracks and bubbles) occur between adjacent wafers
Solution Approach 1:
The patent performs edge defect inspection using C-mode scanning acoustic microscope before completing the full wafer stack fabrication process. By detecting and documenting edge defects at an early stage, the method enables preliminary identification of problematic areas that can then be addressed through selective trimming or process optimization, preventing further resource investment in defective structures
Solution Approach 2:
The patent converts the harmful edge defects into useful information by using acoustic microscopy to detect and locate them. The detected defect positions are then used to guide selective trimming operations, where only the necessary portions containing defects are removed. This transforms the initial harm (edge defects) into a benefit (precise defect removal with minimal material loss)
2Reliability
If trimming process is performed to remove edge defects, then the defect removal effectiveness is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies trimming operations selectively only to the radial extent necessary to remove detected edge defects, rather than performing uniform trimming across the entire wafer edge. The trimming width is precisely controlled based on the measured distance from the wafer edge to the defect location, ensuring that material removal is localized exactly where needed and no more
Solution Approach 2:
The patent implements a feedback loop where edge defect inspection results directly inform the trimming process parameters. The measured defect distances from acoustic microscopy provide feedback that determines the precise trimming width, creating a closed-loop system that automatically adjusts manufacturing parameters based on actual defect conditions
3Reliability
If the trimming width is increased to ensure complete defect removal, then the defect removal completeness is improved, but the wafer area loss increases
Solution Approach 1:
The patent applies a trimming width that is partially excessive relative to the minimum needed, by adding a safety margin to the measured defect distance. This ensures complete defect removal while minimizing unnecessary material loss, optimizing the balance between removal completeness and material conservation
Solution Approach 2:
The patent dynamically adjusts the trimming width parameter based on the measured defect characteristics. By changing the trimming parameter from a fixed value to a variable determined by actual defect measurements, the system optimizes material removal to match the actual defect extent, reducing unnecessary wafer area loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively removes edge defects, improving yield by ensuring complete removal of cracks and bubbles while preventing metal exposure during subsequent processes.
Implementation Method 1
A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect
Data Source
AI summary
A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.