Wafer Stack Vertical Interconnections for Defect Localization
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Solution Overview
Problem
In the context of semiconductor technology, as chip structures become three-dimensional for high-degree integration and performance, wafer-level packaging increases the likelihood of chip failures due to stacked layers, making it difficult to identify which layer is defective during electrical performance testing.
Innovation Solution
A bonding structure and method that form a wafer stack with electrical vertical interconnections, including thorough, partial, and single vertical interconnections, allowing for testing of electrical performance across multiple layers or individual layers, enabling the location of defective chips within the stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wafer-level packaging technology is used to bond multiple wafers in sequence to achieve high-degree integration and high performance, then chip response speed is increased and chip dimension is reduced, but the probability of chip failures increases and it becomes difficult to determine which chip layer results in the failure
Solution Approach 1:
The patent divides the wafer stack into multiple independently testable units by implementing different interconnection strategies. Through-silicon vias (TSVs) are selectively configured to connect only certain chip layers to the substrate, creating separable testing zones. This allows individual chip layers to be electrically isolated and tested independently, enabling failure localization without requiring complete stack disassembly.
Solution Approach 2:
The patent introduces an intermediary testing mechanism using selectively configured TSVs and interconnection layers that act as mediators between the chip stack and substrate. These intermediaries enable electrical access to specific chip layers without direct physical access, allowing testers to probe individual layers through the substrate interface and identify failures without disturbing the bonded stack structure.
2Reliability
If electrical performance testing is performed on a fabricated chip stack to identify failures, then chip reliability can be assessed, but it is difficult to determine which chip layer results in the failure
Solution Approach 1:
The patent segments the electrical testing function by configuring different TSVs to connect to different chip layers through selective etching and filling processes. This creates distinct electrical pathways that can be independently activated during testing, allowing the test system to probe specific layers and identify which segment contains the failure based on test results from each pathway.
Solution Approach 2:
The patent adds a vertical dimension to electrical testing by using TSVs that penetrate through the substrate and interconnection layers to reach specific chip layers. This three-dimensional interconnection approach allows electrical access to internal layers without horizontal disassembly, enabling depth-resolved testing where failures can be localized to specific vertical positions in the stack.
3Adaptability or versatility
If multiple chip layers are stacked to achieve high-degree integration, then more I/Os and functionality are provided, but the complexity of identifying defective chips increases
Solution Approach 1:
The patent applies segmentation to the interconnection architecture by implementing separate TSV pathways for different chip layers. Each layer can be electrically accessed through its dedicated TSV route, creating modular testing units. This segmented approach maintains the high integration benefit of multiple layers while reducing identification complexity by allowing systematic isolation and testing of each layer independently.
Data Source
AI summary
A bonding structure and a method for manufacturing the same. The bonding structure includes a wafer stack formed by multiple wafers that are bonded in sequence, where: chip stacks are arranged in an array in the wafer stack, and each of the chip stacks includes multiple layers of chips that are bonded in sequence; electrical vertical interconnections are formed in each of the chip stacks; and the electrical vertical interconnections include a thorough vertical interconnection that is electrically connected to an interconnection layer in each of the multiple layers, and a partial vertical interconnection that is electrically connected to the interconnection layer in each of a part of the multiple layers and/or a single vertical interconnection that is electrically connected to the interconnection layer in a single layer of the multiple layers.