Wafer Stack Test Pad Layout to Limit Warpage and Yield Loss
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Solution Overview
Problem
Conventional wafer-to-wafer bonding techniques face issues with warpage and yield degradation as the number of stacked wafers increases, limiting the number of dies and wafers that can be integrated in semiconductor devices.
Innovation Solution
A method involving pre-forming metal pads on the first wafer structure before stacking, followed by testing and screening die stacks to ensure only qualified die stacks are integrated, and using hybrid bonding to connect them, thereby mitigating warpage and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked wafers is increased to achieve higher integration, then the performance and functionality of the semiconductor device are improved, but the warpage of the wafer stack structure becomes more serious
Solution Approach 1:
The method performs preliminary actions including forming metal pads on the first wafer structure before stacking, conducting first test on second wafers before stacking to identify good dies, and preparing bonding interfaces in advance. These preliminary actions enable subsequent stacking of multiple wafers without exacerbating warpage, as the structural preparations are made before the stacking process begins
Solution Approach 2:
The wafer stacking process is segmented into distinct stages: preparing first wafer structure with metal pads, selecting and stacking second wafers that passed first test, conducting second test on die stacks, and dicing only the passing die stacks. This segmentation allows quality control at each stage, preventing warpage accumulation and enabling integration of more dies while maintaining structural integrity
2Quantity of substance
If the number of stacked wafers is increased to achieve higher integration, then the device complexity is improved, but the yield of the wafer stack structure decreases
Solution Approach 1:
The method conducts first test on second wafers before stacking to identify good dies, and performs second test on die stacks after stacking but before dicing. This preliminary testing approach ensures that only wafer stacks containing good dies are diced and processed further, significantly improving yield while enabling stacking of more wafers
Solution Approach 2:
The method implements feedback mechanisms through first test and second test that provide information about die quality at different stages. The first test feedback guides wafer selection before stacking, and the second test feedback determines which die stacks proceed to dicing. This feedback loop maintains high yield even as the number of stacked wafers increases
3Adaptability or versatility
If wafer-to-wafer bonding is used to integrate multiple dies, then heterogeneous integration is achieved, but the number of stacked dies is greatly limited due to warpage and yield issues
Solution Approach 1:
The method forms metal pads on the first wafer structure before stacking, conducts first test on second wafers before stacking, and performs second test on die stacks after stacking. These preliminary actions enable heterogeneous integration of multiple different types of dies while controlling warpage and maintaining yield, thereby increasing the number of stacked dies beyond conventional limits
Solution Approach 2:
The method changes the process parameters by introducing intermediate testing stages (first test before stacking, second test after stacking) and preparing metal pads in advance. These parameter changes enable better control over warpage and yield, allowing heterogeneous integration of more dies than conventional wafer-to-wafer bonding methods
Data Source
AI summary
A semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a first wafer structure and at least one die stack layer stacked on a second side of the first wafer structure. The die stack has first test pad and second test pad, which can be used to test and screen the die in the die stack and the die stack, contributing to increased yield of the semiconductor device. Additionally, metal pad may be formed on a first side of the first wafer structure before the die stack is stacked on the first wafer structure, avoiding warpage or other distortion possibly otherwise caused by high-temperature treatment if they are formed after the die stack is stacked. This facilitates stacking of more dies and/or wafers together. The semiconductor device is obtainable according to the method.