3D Wafer Stack Via Metallization with Oxide Diffusion Barrier
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Solution Overview
Problem
Current three-dimensional integrated circuit fabrication techniques face challenges in wafer stacking and interconnection, particularly due to copper diffusion during heat bonding, uneven metallization, and the need for additional processing steps, which can lead to device failures and increased costs.
Innovation Solution
A method for forming a three-dimensional wafer stack with a single metallized via through the stack, using aligned silicon wafers with oxide layers for bonding and copper electroplating to create a continuous, homogeneous metallization path without copper diffusion, allowing for variable cross-sectional shapes and reduced processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If heat is used to bond the wafers, then the wafers are adhered together, but metal ions may diffuse into the wafer-to-wafer bonding region causing device failure
Solution Approach 1:
An oxide layer (mediator material) is formed on the wafer surfaces before bonding. This oxide layer acts as a diffusion barrier that prevents copper ions from migrating into the bonding region during the bonding process, while still allowing the wafers to bond effectively. The oxide layer is selectively removed from via regions to allow metal-to-metal bonding while maintaining the barrier in other areas.
Solution Approach 2:
The oxide layer is selectively removed from via regions using targeted etching processes, creating local variations in oxide presence. This allows metal-to-metal bonding in via regions (where conductors need to connect) while maintaining oxide protection in non-via regions (where diffusion prevention is critical).
2Reliability
If via metallization is performed on each individual wafer followed by inter-wafer via bonding, then vertical interconnection is achieved, but expensive and time-consuming processing steps are added
Solution Approach 1:
Multiple individual wafer via bonding operations are merged into a single batch process. Wafers are stacked in sequence with aligned vias, and a single bonding operation bonds all wafers simultaneously through the stacked configuration. This combining of operations eliminates the need for sequential pairwise bonding, dramatically reducing processing time and cost while maintaining reliable vertical interconnection.
Solution Approach 2:
The bonding process is segmented into two distinct phases: (1) individual wafer preparation with via metallization and oxide formation, and (2) batch stacking and bonding of multiple wafers. This segmentation allows the metallization work to be done on individual wafers in parallel, while the bonding is performed as an efficient batch operation, optimizing both reliability and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and stress-minimized bonding of wafers with uniform metallization, reducing the risk of device failure and processing time, while avoiding copper diffusion issues and enabling the formation of complex via cross-sectional shapes.
Implementation Method 1
copper electroplating to form a continuous and homogeneous metallization path through the three-dimensional wafer stack
Data Source
AI summary
The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and silicon wafers. Each wafer has one or more integrated circuits formed thereon. One or more through-vias are formed in each silicon wafer followed by oxide formation on at least an upper and lower surface of the silicon wafer. The wafers are aligned such that each wafer through via is aligned with a corresponding through via in adjacent stacked wafers. Wafers are bonded to form a three-dimensional wafer stack having one or more stack vias formed from the alignment of individual wafer vias. Via metallization is performed by depositing a seed layer in each of the stack vias followed by copper electroplating to form a continuous and homogeneous metallization path through the three-dimensional wafer stack.