Wafer-Stacked Cascode HEMT Structure for High Breakdown Voltage

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Solution Overview

Problem

Existing high voltage transistor devices face challenges in achieving high breakdown voltages without increasing layer thickness, which can lead to higher manufacturing costs and defects, and require efficient heat dissipation and reduced area and resistance.

Innovation Solution

A cascode HEMT device is formed by bonding HEMT devices on separate wafers, allowing for a breakdown voltage of 1200 V or greater without thick channel layers, reducing device area, and improving thermal performance and electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If layer thickness is increased to achieve high breakdown voltage, then breakdown voltage is improved, but manufacturing cost and defects increase

Engineering Contradiction:
Improvebreakdown voltageVSAvoidmanufacturing cost and defects
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The device is divided into two separate wafers, each containing a HEMT structure. By bonding the wafers together, the effective breakdown voltage is doubled without increasing the thickness of individual channel layers. This segmentation allows achieving high breakdown voltage (1200V or greater) while maintaining thin channel layers that are easier and cheaper to manufacture with fewer defects.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If device area is reduced, then integration density is improved, but heat dissipation becomes more difficult

Engineering Contradiction:
Improvedevice areaVSAvoidheat dissipation
Core Design Contradiction:
Area of stationary objectVSTemperature

Solution Approach 1:

The patent transitions from a planar heat dissipation approach to a three-dimensional stacked architecture. By bonding two wafers together with HEMT devices on each, heat can be dissipated from both top and bottom surfaces of the stacked structure. This vertical stacking reduces the footprint area while maintaining effective heat dissipation through multiple surfaces.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If wafer bonding is performed, then device integration is improved, but process complexity increases

Engineering Contradiction:
Improvedevice integrationVSAvoidprocess complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The HEMT devices are fabricated and prepared on separate wafers before bonding. All necessary device formation steps (channel layer deposition, gate structures, contacts) are completed on individual wafers while they are still accessible from one side. This preliminary action simplifies the bonding process and reduces overall process complexity compared to attempting to form and bond devices simultaneously.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The cascode HEMT device achieves high breakdown voltage with reduced size and cost, enhanced thermal behavior, and lower resistance, while maintaining efficient heat dissipation and improved electrical connections.

Implementation Method 1

bonding HEMT devices on separate wafers

Methodology Applied
Scientific EffectBonding: Welding

Data Source

PatentUS12451419B2Wafer-on-wafer cascode HEMT device
Publication Date: 2025.10.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12451419B2 patent drawing
  • US12451419B2 patent drawing
  • US12451419B2 patent drawing

AI summary

A semiconductor device includes a first semiconductor structure including a first high electron mobility transistor (HEMT) device, wherein the first HEMT device includes a first gate, a first source, and a first drain; and a second semiconductor structure stacked above and bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second HEMT device and a third HEMT device, wherein the second HEMT device includes a second gate, a second source, and a second drain that is electrically connected to the first source, wherein the third HEMT device includes a third gate, a third source, and a third drain that is electrically connected to the first gate.