Wafer Stacked Package Vertical Heat Emission Path
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Solution Overview
Problem
Conventional semiconductor packages with vertically stacked chips face heat dissipation challenges due to adhesive blocking heat conduction, leading to reliability issues, especially in high-power devices like DDR DRAMs and microprocessors.
Innovation Solution
A wafer stacked semiconductor package with a vertical heat emission path is introduced, featuring a substrate with semiconductor chips stacked vertically, a cooling through-hole penetrating subsequent chips, an evaporation unit, a condensation unit, and a coolant filling the sealed path, enhancing heat dissipation through evaporation and condensation of the coolant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If adhesive is used for bonding stacked semiconductor chips, then mechanical strength and electrical connection are improved, but heat conduction between chips deteriorates due to adhesive blocking heat paths
Solution Approach 1:
The bonding structure is segmented into multiple functional layers: adhesive layers for mechanical bonding, and separate heat conduction paths (through-holes filled with conductive material) for thermal management. This segmentation allows the adhesive to perform its bonding function without compromising heat conduction, as the heat paths are provided by the through-hole structures rather than relying on the adhesive's thermal conductivity.
Solution Approach 2:
Heat conduction paste or conductive material is introduced as an intermediary substance within the through-holes to facilitate heat transfer between chips. This intermediary material provides a dedicated thermal conduction path that complements the mechanical bonding function of the adhesive, resolving the conflict between bonding strength and heat conduction.
2Productivity
If multiple high-power semiconductor chips are vertically stacked to improve integration density, then device functionality and integration are improved, but heat dissipation capability deteriorates due to heat accumulation in the middle of the stack
Solution Approach 1:
Heat dissipation is transitioned from a two-dimensional surface-level process to a three-dimensional vertical process. Through-holes penetrating the chips create vertical heat conduction paths that extend through the entire stack, allowing heat to be conducted upward and outward from the middle chips rather than being trapped in horizontal planes. This dimensional change enables effective heat management in high-density vertical stacks.
Solution Approach 2:
Different regions of the chip structure are assigned different functional qualities: the through-holes and their filled materials provide high thermal conductivity paths, while the adhesive layers provide mechanical bonding. This local differentiation of material properties ensures that heat conduction occurs through optimized paths without compromising the overall structural integrity of the stack.
3Ease of manufacture
If conventional WSP structure without vertical heat path is used, then manufacturing simplicity is maintained, but heat emission efficiency deteriorates resulting in temperature exceeding 85°C at power consumption of 0.2W or more
Solution Approach 1:
Heat conduction paths (through-holes) are formed and prepared in advance during the chip fabrication process, before the stacking and bonding operations. This preliminary preparation of thermal paths ensures that heat dissipation capability is built into the chip structure itself, allowing the final assembly to achieve reliable thermal management without adding complex post-assembly cooling systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces heat buildup and quickly dissipates heat, improving the thermal reliability of the semiconductor package by providing a heat emission path with thermal conductivity characteristics one hundred times greater than conventional structures.
Implementation Method 1
an evaporation unit positioned on the lowest semiconductor chip being stacked
Implementation Method 2
a condensation unit positioned on the top of the semiconductor chips and sealing an upper part of the cooling though-hole
Data Source
AI summary
A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.