Wafer Stacking Package Method for Reduced Chip Damage
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Solution Overview
Problem
Conventional flip chip interconnect technologies face challenges in efficiently stacking and connecting chips due to limitations in package area and signal transferring path, leading to potential chip damage and wafer breakage, and require labor-intensive alignment processes.
Innovation Solution
A wafer stacking package method involving pre-cutting a first wafer into independent chips and forming an adhesion layer on a second wafer, with specified depth cuts to separate chips, allowing for overlapping and thinning to create independent stack chips with reduced chip damage and simplified alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip chip interconnect technology is used with multiple chips stacked, then high pin contact and short signal transferring path are achieved, but package area increases and alignment complexity increases
Solution Approach 1:
Multiple chips are stacked vertically to merge their functions into a single compact package, achieving high pin contact and short signal paths while reducing the overall package area compared to lateral arrangements
Solution Approach 2:
The patent transitions from a two-dimensional lateral chip arrangement to a three-dimensional vertical stack configuration, allowing multiple chips to occupy the same footprint area while maintaining electrical connectivity
2Reliability
If multiple chips are stacked with precise alignment, then electrical connection is achieved, but chip damage and wafer breakage occur due to handling complexity
Solution Approach 1:
Chips are pre-cut from the wafer to individual units before stacking, and alignment features are pre-formed on the chips, allowing for easier and more reliable alignment during the stacking process without causing damage
Solution Approach 2:
An adhesive layer is introduced as an intermediary between chips during stacking, providing a buffer that facilitates alignment and reduces mechanical stress that could cause chip or wafer breakage
3Manufacturing precision
If manual alignment process is used for chip stacking, then precise positioning is achieved, but labor intensity and process time increase
Solution Approach 1:
The stacking structure is designed with self-aligning features where chips automatically position themselves relative to each other through geometric constraints and alignment features, eliminating the need for manual alignment operations
Solution Approach 2:
Multiple stacking operations are combined into a single automated process step, where multiple chips are stacked and aligned simultaneously rather than requiring separate manual alignment operations for each chip
Data Source
AI summary
A method of wafer stacking packaging. The method comprises providing a die array including a plurality of singulated first dies cut from a first wafer; providing a second wafer with inseparate the second dies and an adhesive layer on an active surface thereof; pre-cutting the second wafer to a specified depth from the active surface thereof; stacking the active surface of second wafer onto a backside of the first dies, wherein each of the second dies only stack on one of the first dies; thinning the second wafer from the backside thereof to form a plurality of singulated the second dies stacked on the first dies simultaneously.