Wafer Stacking via Redistribution Layers and TSVs
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Solution Overview
Problem
The existing die-to-die or die-to-wafer bonding process in IC manufacturing is inefficient, leading to high costs, susceptibility to connection errors, and low production yield due to the need for advance TSV and micro bump fabrication for each die, which can disrupt electrical connections between layers.
Innovation Solution
A wafer stacking method involving the sequential fabrication of redistribution layers (RDLs) on wafers, bonding wafers together before forming through silicon vias (TSVs), and establishing signal connections through the RDLs, eliminating the need for micro bumps and reducing alignment and connection errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die-to-die or die-to-wafer bonding process is used with TSV and micro bump fabrication for each die, then electrical connections between dies can be established, but the process efficiency is low and manufacturing cost is high
Solution Approach 1:
The patent inverts the conventional sequence by fabricating TSVs and micro bumps on the wafer level before bonding, rather than after die separation. This allows the entire wafer to be processed simultaneously, dramatically improving productivity while maintaining connection reliability through the pre-established interconnect structures.
Solution Approach 2:
The patent performs preliminary fabrication of TSVs, lower RDLs, and micro bumps on the wafer before the bonding process. This preliminary action ensures that all electrical connection elements are ready in advance, enabling high-speed bonding without compromising connection quality, thus resolving the contradiction between speed and reliability.
2Reliability
If TSV and micro bumps are fabricated for each die in advance, then inter-layer electrical connections can be established, but positioning or connection errors occur and production yield decreases
Solution Approach 1:
The patent merges the fabrication of TSVs, lower RDLs, and micro bumps into a single integrated wafer-level process that occurs before bonding. This combination ensures that all interconnect elements are precisely positioned relative to each other on the same wafer, eliminating alignment errors that would occur if these elements were fabricated separately on individual dies.
Solution Approach 2:
By performing all interconnect fabrication (TSV etching, RDL deposition, micro bump formation) as preliminary actions on the wafer before bonding, the patent ensures that positioning accuracy is maintained throughout the process. The preliminary fabrication establishes fixed geometric relationships that cannot be compromised during subsequent bonding operations.
3Reliability
If conventional die stacking method is used, then mechanical and electrical connections can be established, but the process is complex and production yield is low
Solution Approach 1:
The patent combines multiple fabrication steps (TSV formation, lower RDL deposition, micro bump creation) into a single integrated wafer-level process flow. This merging reduces the total number of separate process modules required, simplifying the overall fabrication complexity while maintaining reliable electrical connections through the unified structure.
Solution Approach 2:
The patent transitions from three-dimensional die stacking with complex individual die preparation to a two-dimensional wafer-level fabrication approach. By performing all interconnect fabrication on the flat wafer surface before bonding, the patent reduces process complexity while achieving the same three-dimensional electrical connection functionality through a different dimensional approach.
Data Source
AI summary
A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer having an upper surface comprising a first bonding pad configured to connect to a first signal; fabricating a first lower redistribution layer (RDL) and a first upper RDL on the first wafer, with the first lower RDL including a first wiring connected to the first bonding pad, the first upper RDL including a second wiring connected to the first wiring, and the second wiring having a first landing pad; bonding a second wafer on the first upper RDL, wherein an upper surface of the second wafer includes a second bonding pad configured to connect to a second signal and located corresponding to the first bonding pad; and fabricating a first through silicon via (TSV) connected to the first landing pad. The wafer stacking method improves the manufacturing yield of a die.