Wafer Stage Electrode Voltage Control for Lithography Flatness
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Solution Overview
Problem
Current lithography processes face challenges in accurately patterning semiconductor devices with smaller critical dimensions and increased complexity, leading to reduced production yield and quality.
Innovation Solution
A lithographic system and method that utilizes a wafer stage with electrically isolated electrodes to apply controlled voltages for electrostatic clamping, adjusting the wafer's topology to improve flatness and secure it during exposure, thereby enhancing the precision of the lithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography processes are used, then manufacturing complexity is reduced, but manufacturing precision deteriorates due to inaccurate patterning of small features
Solution Approach 1:
The patent applies preliminary action by measuring the topology of the semiconductor wafer before the lithography exposing process and using this information to adjust the wafer stage electrodes. This pre-adjustment of wafer flatness ensures accurate patterning is achieved without increasing the complexity of the lithography process itself, as the topology measurement and electrode adjustment are performed as preparatory steps before exposure.
2Manufacturing precision
If wafer flatness is not adjusted, then device complexity is reduced, but manufacturing precision deteriorates due to overlay errors
Solution Approach 1:
The patent applies local quality by using multiple independently controllable electrodes positioned at different locations on the wafer stage. Each electrode can be adjusted independently to compensate for local variations in wafer topology, allowing precise control of flatness in specific regions without requiring complete redesign of the entire wafer stage system.
Solution Approach 2:
The patent applies parameter changes by adjusting the voltage applied to the wafer stage electrodes to control the electrostatic clamping force. By varying the voltage parameter, the system can dynamically adjust the degree of clamping and resulting wafer flatness, enabling precise control of overlay accuracy without adding mechanical complexity to the wafer stage structure.
3Manufacturing precision
If electrostatic clamping is not used, then device complexity is reduced, but manufacturing precision deteriorates due to inaccurate wafer positioning
Solution Approach 1:
The patent applies mechanics substitution by replacing traditional mechanical clamping mechanisms with an electrostatic field-based system. Instead of using mechanical springs, screws, or pneumatic elements to hold the wafer, the system uses voltage-controlled electrostatic forces to achieve both positioning and flatness adjustment, thereby improving precision while avoiding the added complexity of mechanical adjustment mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the flatness of semiconductor wafers, reduces overlay errors, and increases the yield of semiconductor wafers by ensuring accurate patterning and exposure, even with complex device designs.
Implementation Method 1
A lithographic system and method that utilizes a wafer stage with electrically isolated electrodes to apply controlled voltages for electrostatic clamping, adjusting the wafer's topology to improve flatness and secure it during exposure
Data Source
AI summary
A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer over a wafer stage. The method also includes supplying an initial voltage to a plurality of electrodes of the wafer stage based on a topology of the semiconductor wafer, wherein the electrodes of the wafer stage are electrically isolated from each other. The method further includes measuring an adjusted topology of the semiconductor wafer after the initial voltage is supplied. In addition, the method includes supplying different first adjusted voltages to the electrodes of the wafer stage according to the adjusted topology of the semiconductor wafer.