Wafer Stress Control via Backside Deep Trench Patterning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor fabrication, the shrinking feature sizes of IC chips lead to increased challenges in controlling topography and overlay errors, which affect product yield due to stress issues from deep trenches in circuit elements.
Innovation Solution
A method is developed to form corresponding mirror patterns of deep trenches on both sides of a semiconductor substrate, with the back side trenches covered in polysilicon, to balance stresses and reduce warping, thereby mitigating topography and overlay errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep trenches are formed in circuit elements to achieve greater device densities, then device density is improved, but substrate warping and stress issues worsen
Solution Approach 1:
The patent applies the counterweight principle by forming dummy deep trenches on the back side of the substrate that mirror the front side trenches. These dummy trenches act as counterweights to balance the stress and prevent substrate warping caused by the functional deep trenches on the front side, thereby resolving the contradiction between achieving high device density and maintaining substrate stability.
Solution Approach 2:
The patent uses asymmetry by creating a symmetric stress balance through asymmetric placement - functional deep trenches are formed only on the front side for device functionality, while corresponding dummy trenches are formed on the back side. This asymmetric approach to achieving symmetry in stress distribution allows high device density on the front side while preventing warping through back side compensation.
2Quantity of substance
If feature sizes are reduced to increase device density, then device density is improved, but control of topography and overlay errors worsens
Solution Approach 1:
By forming dummy deep trenches on the back side that mirror the front side trenches, the patent creates a counterbalancing effect that neutralizes topography variations. This stress balancing approach maintains uniform substrate topology even as feature sizes shrink and device density increases, thereby improving topography control alongside device density.
Solution Approach 2:
The patent achieves equipotentiality in terms of stress distribution by creating symmetric stress conditions on both sides of the substrate. The dummy trenches on the back side create an equipotential stress state that counteracts the stress from functional trenches on the front side, maintaining uniform topography and reducing overlay errors during fabrication.
3Reliability
If deep trenches are formed on the front side for circuit elements, then device functionality is improved, but stress imbalance and warping worsen
Solution Approach 1:
The patent directly applies the counterweight principle by forming dummy deep trenches on the back side of the substrate that correspond to the functional deep trenches on the front side. These dummy trenches provide counterbalancing stress that prevents warping and maintains substrate flatness, allowing functional devices to operate reliably without stress-induced performance degradation.
Solution Approach 2:
The patent uses inversion by addressing the stress problem from the opposite side of the substrate. Instead of modifying the functional front side trenches, the solution is implemented on the back side by forming dummy trenches that mirror the front side pattern. This inverted approach to stress management preserves device functionality while eliminating stress imbalance.
Data Source
AI summary
Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.