Wafer Stress-Inducing Structures for Backside Warp Reduction
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Solution Overview
Problem
Integrated circuit wafers with deep trench capacitors often experience severe bowing due to thermal expansion mismatch, which interferes with subsequent processing steps like chemical mechanical polishing, especially in 3D IC devices.
Innovation Solution
Forming structures with tensile stress on the backside of the wafer, including trenches filled with tensile materials or compressive films on the frontside, to counteract the bowing stress induced by deep trench capacitors, thereby reducing wafer bow to acceptable levels for further processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep trench capacitors are formed on the front side of the wafer to increase device density, then the integrated circuit component density is improved, but the wafer experiences severe bowing due to thermal expansion mismatch
Solution Approach 1:
The patent applies the counterweight principle by forming stress-inducing structures on the back side of the wafer that generate mechanical stress opposite to the bowing stress caused by deep trench capacitors. These structures act as a counterbalancing force, reducing net wafer bow by at least 50% while preserving the high-density capacitor structure on the front side.
Solution Approach 2:
The patent transitions from two-dimensional capacitor placement to three-dimensional stress management by adding stress-inducing structures on the back side of the wafer. This dimensional extension allows independent control of wafer curvature without affecting the front-side capacitor density, effectively decoupling the density and warping issues.
2Quantity of substance
If deep trench capacitors with multiple conductive layers are formed to further increase density, then the integrated circuit component density is improved, but the wafer bowing becomes particularly severe and adversely affects subsequent processing
Solution Approach 1:
The stress-inducing structures on the back side generate counterbalancing mechanical stress that offsets the severe bowing caused by multi-layer deep trench capacitors. This reduces wafer bow to acceptable levels, enabling uniform chemical mechanical polishing and preventing processing disruptions.
Solution Approach 2:
The patent applies preliminary anti-action by forming stress-inducing structures before subsequent processing steps like chemical mechanical polishing. This preemptive stress balancing prevents bowing-related processing defects before they occur, ensuring manufacturing precision is maintained throughout the fabrication sequence.
3Shape
If stress-inducing structures are formed on the back side of the wafer to counteract bowing stress, then the wafer bow is reduced to acceptable levels, but the device structure becomes more complex
Solution Approach 1:
The stress-inducing structures are localized to specific regions on the back side of the wafer, corresponding to the locations of deep trench capacitors on the front side. This localized approach provides targeted stress compensation without adding complexity across the entire wafer surface, maintaining manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress-balancing structures effectively reduce wafer bow by at least 50%, allowing for uniform chemical mechanical polishing and preventing processing disruptions, even in high-density 3D IC devices.
Implementation Method 1
severe bowing due to thermal expansion mismatch
Implementation Method 2
forming structures with tensile stress on the backside of the wafer... to counteract the bowing stress induced by deep trench capacitors
Data Source
AI summary
Some embodiments relate to a method. In this method, a semiconductor wafer having a frontside and a backside is received. A frontside structure is formed on the frontside of the semiconductor wafer. The frontside structure exerts a first wafer-bowing stress that bows the semiconductor wafer by a first bow amount. A characteristic is determined for one or more stress-inducing films to be formed based on the first bow amount. The one or more stress-inducing films are formed with the determined characteristic on the backside of the semiconductor wafer and/or on the frontside of the semiconductor wafer to reduce the first bow amount in the semiconductor wafer.