Semiconductor Wafer Stress Generating Layer Warping Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
When forming Group-III nitride semiconductor layers on Si wafers, warping and crystal quality uniformity issues arise due to thermal expansion coefficient differences, making it challenging to maintain reliable withstand voltage and in-plane physical property uniformity, especially for large wafers.
Innovation Solution
A semiconductor wafer structure comprising a silicon wafer with a nitride crystal layer that includes a reaction suppressing layer, a stress generating layer, and an active layer, where the reaction suppressing layer is positioned closest to the silicon wafer, and the stress generating layer has a two-layer stack structure with different bulk crystal lattice constants to generate compressive stress, balancing thermal expansion and enhancing crystallinity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a Group-III nitride semiconductor layer is formed on a Si wafer, then the productivity and cost-effectiveness are improved, but the wafer warping and crystal quality uniformity deteriorate due to thermal expansion coefficient differences
Solution Approach 1:
The patent segments the buffer layer into multiple distinct layers with different compositions and functions: a reaction suppressing layer (AlN or AlGaN) to prevent Si-Ga reactions, a stress generating layer (AlN/AlGaN superlattice) to control wafer warping, and a crystallinity improving layer (GaN or AlGaN) to enhance crystal quality. This segmentation allows each layer to address specific problems independently while working together to achieve overall device performance.
Solution Approach 2:
The patent introduces intermediary buffer layers between the Si wafer and the Group-III nitride semiconductor layer. These buffer layers act as mediators that gradually transition the lattice mismatch and thermal expansion differences between Si and GaN, reducing dislocation density and improving crystal quality uniformity across the wafer surface.
2Productivity
If the wafer diameter is increased to improve productivity, then the output per batch is increased, but the warping and in-plane physical property uniformity worsen
Solution Approach 1:
The patent applies local quality by creating a radial gradient in the buffer layer structure, where the composition and thickness of buffer layers vary from the wafer center to the edge. This allows the buffer layers to locally compensate for the increased stress and lattice mismatch that occur at larger radial distances from the center, maintaining uniform crystal quality across the entire large-diameter wafer surface.
3Object-affected harmful factors
If a reaction suppressing layer is added to protect the Si wafer surface, then the wafer protection is improved, but the device complexity increases
Solution Approach 1:
The patent designs the buffer layer structure to be multi-functional: the reaction suppressing layer not only prevents Si-Ga reactions but also serves as a nucleation layer for subsequent epitaxial growth, while the stress generating layer simultaneously controls wafer warping and improves crystal orientation. This multi-functionality reduces the need for separate dedicated layers, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces warping, achieves in-plane uniformity of physical properties, and ensures high withstand voltage and mobility while protecting the silicon wafer surface, even for large diameters, by effectively managing stress and crystal growth.
Implementation Method 1
the stress generating layer has a two-layer stack structure with different bulk crystal lattice constants to generate compressive stress, balancing thermal expansion and enhancing crystallinity
Implementation Method 2
warping and crystal quality uniformity issues arise due to thermal expansion coefficient differences
Implementation Method 3
a reaction suppressing layer configured to suppress reaction between a silicon atom and a Group-III atom
Implementation Method 4
Attempts have been made to develop techniques of growing Group-III nitride semiconductor crystals on Si wafers
Data Source
AI summary
Provided is a semiconductor wafer in which a nitride crystal layer on a silicon wafer includes a reaction suppressing layer to suppress reaction between a silicon atom and a Group-III atom, a stress generating layer to generate compressive stress and an active layer in which an electronic element is to be formed, the reaction suppressing layer, the stress generating layer and the active layer are arranged in an order of the reaction suppressing layer, the stress generating layer and the active layer with the reaction suppressing layer being positioned the closest to the silicon wafer, and the stress generating layer includes a first crystal layer having a bulk crystal lattice constant of al and a second crystal layer in contact with a surface of the first crystal layer that faces the active layer, where the second crystal layer has a bulk crystal lattice constant of a2 (a1<a2).