Wafer Substrate Edge Trimming for Semiconductor Package Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for manufacturing semiconductor packages with stacked semiconductor chips are prone to damage during the manufacturing process, affecting the mechanical and electrical reliability of the final product.
Innovation Solution
A method involving the formation of a wafer substrate with through electrodes, trimming of edges, application of protection and adhesive layers, and a molding element to cover the semiconductor chips, ensuring the semiconductor wafer substrate is not exposed and thus protected from damage during handling and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are stacked on a wafer substrate using conventional methods, then high integration and large capacity are achieved, but the substrate and chips become susceptible to damage during manufacturing
Solution Approach 1:
The method performs preliminary protective actions before the stacking process by forming a protection layer on the wafer substrate surface and trimming the substrate edges to create a stepped structure. This preliminary preparation ensures that the substrate is protected from damage before chips are mounted, resolving the contradiction between achieving high integration and preventing manufacturing damage.
Solution Approach 2:
The protection layer acts as a cushioning element that absorbs mechanical stresses and prevents direct contact between handling tools and the fragile wafer substrate. The trimmed edges create a stepped structure that provides mechanical support and reduces stress concentration points, thereby cushioning the substrate against damage during the stacking process.
2Ease of manufacture
If the wafer substrate is fully exposed during stacking, then chip mounting is simplified, but the substrate edges are vulnerable to damage
Solution Approach 1:
The wafer substrate surface is segmented into different levels through edge trimming, creating a stepped structure with a first surface for chip mounting and a second surface with exposed edges. This segmentation allows the main mounting area to remain accessible while protecting the vulnerable edge regions, resolving the contradiction between manufacturing ease and structural strength.
Solution Approach 2:
Different regions of the wafer substrate are given different properties: the first surface maintains a flat, exposed condition for easy chip mounting, while the second surface edges are trimmed and covered with a protection layer to provide local reinforcement. This local differentiation resolves the contradiction by providing ease of manufacture where needed while strengthening vulnerable areas.
3Ease of operation
If protection layers and adhesive layers are applied to cover the substrate, then handling property is improved, but process complexity increases
Solution Approach 1:
The protection layer serves multiple functions simultaneously: it protects the wafer substrate from damage during handling, provides a stable surface for chip mounting, and acts as a base for the adhesive layer. The adhesive layer also serves dual purposes by bonding chips to the substrate and providing additional mechanical support. This multi-functionality improves handling properties while minimizing the increase in process complexity.
Data Source
AI summary
Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.