Wafer-Level Substrate Build-Up Using Embedded E-Bars
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Solution Overview
Problem
Semiconductor device manufacturers face challenges in producing smaller and more complex devices while maintaining efficient manufacturing processes, particularly in the transition from wafer-level substrates to individual semiconductor die.
Innovation Solution
A method is developed for forming a wafer-level substrate by embedding e-bars with conductive pillars onto a carrier, followed by encapsulation and build-up interconnect structures, allowing for cost-effective and efficient signal routing before singulation into individual semiconductor packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional wafer-level substrate manufacturing is used, then manufacturing process is simpler, but manufacturing precision and device complexity are limited
Solution Approach 1:
The substrate manufacturing process is segmented into multiple stages: forming individual e-bars with conductive pillars, embedding them in encapsulant, building up interconnect structures, and finally singulating into individual packages. This segmentation allows each stage to be optimized independently, achieving high precision without overwhelming process complexity.
Solution Approach 2:
The patent transitions from planar wafer-level processing to three-dimensional substrate construction by embedding e-bars vertically within encapsulant and building up multi-layer interconnect structures. This dimensional change enables complex signal routing and higher precision while maintaining manageable process complexity through modular assembly.
2Productivity
If wafer singulation is performed early, then individual devices can be processed, but manufacturing efficiency and cost-effectiveness decrease
Solution Approach 1:
Multiple e-bars are formed, embedded in encapsulant, and have interconnect structures built up on them while still attached to the carrier wafer. This preliminary action performed at the wafer level increases manufacturing efficiency and reduces costs, with singulation delayed until after these value-added steps are complete.
Solution Approach 2:
The patent combines multiple manufacturing operations (e-bar formation, encapsulation, interconnect building) into a unified wafer-level process flow. By merging these steps and performing them before singulation, the method achieves economies of scale and improved productivity while maintaining ease of manufacture.
3Reliability
If e-bars are embedded in encapsulant, then signal routing efficiency improves, but manufacturing process complexity increases
Solution Approach 1:
The encapsulant serves as an intermediary material that embeds and protects the e-bars with conductive pillars. This intermediary structure enables efficient signal routing through the substrate while managing the complexity of integrating conductive elements within the substrate architecture.
Data Source
AI summary
A semiconductor device has an e-bar and an encapsulant deposited over the e-bar. A first surface of the encapsulant is backgrinded to expose the e-bar. A first build-up interconnect structure is formed over the first surface of the encapsulant. A second build-up interconnect structure is formed over a second surface of the encapsulant.