Peripheral Wafer Support Structure for Damage-Free Thinning

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Solution Overview

Problem

The challenge in manufacturing multi-dimensional integrated chips is the damage to semiconductor wafers during thinning and trimming processes due to lack of structural support, leading to reduced yield and device density.

Innovation Solution

Incorporating a support structure between the peripheral regions of bonded wafers to provide structural integrity, mitigating damage during fabrication processes and allowing for the omission of trimming, thereby enhancing reliability and increasing lateral area for semiconductor devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If wafers are thinned during fabrication, then device density is improved, but wafer damage occurs due to lack of structural support

Engineering Contradiction:
Improvedevice densityVSAvoidwafer integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

A support structure is introduced as an intermediary element between the bonded wafer peripheral regions. This support structure provides mechanical reinforcement during the thinning process, preventing wafer damage while allowing high device density in the central region. The support structure acts as a mediator that enables the thinning operation without compromising wafer integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The wafer structure is segmented into a central region for high-density devices and peripheral regions for structural support. The support structure is specifically positioned in the peripheral regions, separating the functional device area from the structural reinforcement area. This segmentation allows the central region to be thinned for high device density while the peripheral support structure maintains overall wafer integrity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If trimming process is performed to remove damaged edges, then wafer quality is improved, but fabrication time and cost increase

Engineering Contradiction:
Improvewafer qualityVSAvoidfabrication time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The support structure is formed in advance during the fabrication process, before the thinning operation. This preliminary action of adding structural support prevents edge damage from occurring in the first place, eliminating the need for subsequent trimming operations. By performing the protective action beforehand, fabrication time is reduced while maintaining wafer quality.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The support structure, which adds material to the wafer periphery, actually prevents the harmful effect of edge damage during thinning. By converting the potential harm of unsupported edges into a beneficial reinforced structure, the need for corrective trimming is eliminated, reducing both time and cost.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Strength

If support structure is added between wafers, then structural integrity is improved, but device area is reduced

Engineering Contradiction:
Improvestructural integrityVSAvoiddevice area
Core Design Contradiction:
StrengthVSArea of stationary object

Solution Approach 1:

The support structure is localized to the peripheral regions of the bonded wafers, while the central region maintains high device density. By applying structural reinforcement only where needed at the edges rather than uniformly across the entire wafer, the device area in the central region is maximized while still providing the necessary structural integrity for thinning operations.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12469817B2Support structure to reinforce stacked semiconductor wafers
Publication Date: 2025.11.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12469817B2 patent drawing
  • US12469817B2 patent drawing
  • US12469817B2 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.