Wafer Temperature Control in Lithography Post-Exposure Bake
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Solution Overview
Problem
In semiconductor manufacturing, lithography processes face critical dimension (CD) variations due to temperature discrepancies in the post-exposure-bake process, where the cooling plate temperature increases between wafers, affecting the uniformity of resist pattern formation.
Innovation Solution
Implementing a controlled pre-cooling and holding strategy for wafers on a cooling plate before transferring them to a baking plate, with adjustable pre-cooling time periods and holding times, and increasing coolant flow rates to maintain wafer temperatures within a predetermined range, ensuring consistent minimum temperatures across multiple wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafers are sequentially processed without pre-cooling, then processing speed is maintained, but wafer temperature varies causing CD variations
Solution Approach 1:
The patent applies pre-cooling action before the post-exposure bake process to reduce wafer temperature to a predetermined range. This preliminary temperature control ensures that subsequent wafers are processed at consistent temperatures, eliminating CD variations caused by temperature differences while maintaining sequential processing efficiency.
Solution Approach 2:
The patent employs temperature sensors to monitor wafer temperature in real-time and provides feedback to the control system. Based on this feedback, the system automatically adjusts cooling plate operation and bake timing to maintain wafer temperature within the predetermined range, ensuring consistent CD across sequentially processed wafers.
2Manufacturing precision
If pre-cooling time is increased to reduce temperature differences, then manufacturing precision improves, but processing time increases
Solution Approach 1:
The patent dynamically adjusts the pre-cooling time based on the specific temperature conditions of each wafer. Rather than using a fixed pre-cooling duration, the system monitors temperature in real-time and terminates cooling when the predetermined temperature range is reached, optimizing the balance between temperature uniformity and processing time.
Solution Approach 2:
The patent changes the temperature parameter dynamically during processing by adjusting cooling plate temperature and pre-cooling duration based on wafer temperature feedback. This parameter adjustment ensures optimal temperature uniformity without excessive processing time extension.
3Measurement precision
If cooling plate temperature is lowered to cool wafers faster, then temperature control precision improves, but energy consumption increases
Solution Approach 1:
The patent applies partial cooling action by using a moderate cooling plate temperature rather than extreme cooling. The cooling is applied just enough to bring wafer temperature into the predetermined range, avoiding excessive energy consumption while achieving sufficient temperature control precision for consistent CD.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces CD variations by maintaining consistent wafer temperatures during the post-exposure-bake process, resulting in more uniform resist pattern formation across sequentially processed wafers.
Implementation Method 1
a cooling plate, wherein the wafer is placed on the cooling plate for a predetermined time period before the post-exposure-bake so that a temperature of the wafer becomes equal to or less than an upper limit of a predetermined temperature range
Implementation Method 2
a baking plate, and the wafer is placed on the baking plate for the PEB when the temperature of the wafer is within a predetermined temperature range
Data Source
AI summary
In a pattern forming method, a resist layer disposed on a wafer is exposed by an energy beam. A post-exposure-bake (PEB) is performed on the wafer with the exposed resist layer by using a PEB apparatus. After the PEB, the exposed resist layer is developed, thereby forming a resist pattern. The PEB apparatus includes a baking plate, and the wafer is placed on the baking plate for the PEB when a temperature of the wafer is within a predetermined temperature range.