Wafer Test Array Layout for Precise Defective Cell Localization
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Solution Overview
Problem
The manufacturing of semiconductor wafers faces challenges in identifying and isolating defective dies during the wafer acceptance test due to the lack of precise methods for pinpointing failure causes, leading to inefficiencies and yield losses in integrated circuit production.
Innovation Solution
A high-density test array is formed on the semiconductor wafer with multiple cells under test, connected through input and output pads, allowing for sequential testing and precise identification of abnormal cells using signal lines, enabling accurate determination of failure locations for physical failure analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional testing methods are used on semiconductor wafers, then the testing process is simpler, but the ability to identify and isolate defective cells is insufficient
Solution Approach 1:
The test array is divided into multiple independently controllable cell units arranged in rows and columns. Each cell can be individually activated and tested through specific signal line combinations, enabling precise localization of defective cells without testing the entire array simultaneously. This segmentation allows the system to achieve high measurement precision while managing complexity through modular testing.
Solution Approach 2:
The patent introduces a two-dimensional addressing scheme using row signal lines and column signal lines to locate cells. By adding the dimensional aspect of row-column intersection, the system can precisely identify any cell's location in the array, transforming a one-dimensional testing approach into a two-dimensional localization system that dramatically improves defective cell identification precision.
2Reliability
If a high-density test array with multiple cells is implemented, then the defective cell identification capability is improved, but the device complexity increases
Solution Approach 1:
The signal lines are designed to serve multiple functions: row signal lines can activate entire rows of cells, column signal lines can activate entire columns, and their intersections enable individual cell selection. This multi-functionality allows the same hardware infrastructure to support various testing modes (individual cell testing, row testing, column testing), improving reliability through comprehensive testing while avoiding the need for separate dedicated circuits for each function.
Solution Approach 2:
The test array structure enables self-identification of defective cells through systematic activation patterns. By sequentially activating cells through row and column signal lines and monitoring output responses, the system automatically locates defective cells without requiring external intervention or complex analysis equipment, thereby improving manufacturing yield through automated defect detection.
3Measurement precision
If sequential testing of multiple cells is performed, then the measurement precision is improved, but the testing time increases
Solution Approach 1:
The testing process uses periodic activation of row and column signal lines in a systematic sequence. Cells are tested in organized cycles through the array, with row lines activated in succession and column lines similarly cycled. This periodic action pattern enables comprehensive coverage of all cells with precise failure location identification while optimizing the testing sequence to minimize total testing time compared to random or unstructured testing approaches.
Data Source
AI summary
A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a first output pad and a second output pad coupled to different cells, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. A first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads to turn on a cell, and a current flowing through the turned-on cell is measured.