Wafer-Level Test Architecture Using Common Scribe Lane Pads
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Solution Overview
Problem
The time required for testing semiconductor devices at a wafer level increases as the number of devices on the wafer increases, due to limitations in the number of probe cards available for simultaneous testing.
Innovation Solution
A test architecture is implemented where common pads in the scribe lane are used to apply test signals simultaneously to multiple semiconductor devices, allowing for the reduction of test time by using these pads to connect multiple dies to input buffers and drivers, enabling efficient testing without the need for individual probe cards for each device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual probe cards are used for each semiconductor device, then testing accuracy is maintained, but test time increases significantly as the number of devices increases
Solution Approach 1:
Multiple individual probe cards are merged into a single shared probe card that can simultaneously access multiple semiconductor devices through common pads. This consolidation maintains testing accuracy while enabling parallel testing of multiple devices, thereby significantly reducing total test time as the number of devices increases.
Solution Approach 2:
The probe card is designed with multi-functionality to serve multiple semiconductor devices simultaneously through shared common pads. This universal probe card structure allows a single probe card to perform testing functions for multiple devices without requiring individual dedicated probe cards for each device, resolving the contradiction between testing accuracy and test time.
2Productivity
If the number of probe cards is increased to test more devices simultaneously, then test time is reduced, but device complexity and manufacturing cost increase
Solution Approach 1:
Multiple probe cards are merged into a single shared probe card that accesses multiple semiconductor devices through common pads. This reduces the quantity of probe cards from equal to the number of devices to a single shared resource, thereby reducing device complexity and manufacturing cost while maintaining high testing efficiency through parallel testing capabilities.
3Loss of time
If common pads are used in scribe lane to connect multiple dies, then test time is reduced through simultaneous testing, but the scribe lane structure must accommodate additional test circuitry
Solution Approach 1:
The scribe lane structure is designed to accommodate multi-functional test circuitry that serves multiple semiconductor devices simultaneously. Common pads in the scribe lane are configured to provide universal access points that can be shared by multiple dies, enabling simultaneous testing while integrating the necessary test circuitry within the scribe lane space without excessive complexity.
Data Source
AI summary
A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.