Semiconductor Wafer Test Pad Protection During Dicing

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Solution Overview

Problem

Existing semiconductor wafer separation methods often result in process defects due to the cutting of test pads during the dicing process, leading to potential electrical shorts and deformation issues when stacking multiple chips.

Innovation Solution

A semiconductor wafer design featuring a protective layer that partially covers the scribe lane region, allowing the test pads to remain coupled with one semiconductor chip while being separated from the other, thereby preventing the cutting of test pads during dicing and reducing the risk of electrical shorts during chip stacking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the test pad is completely exposed in the scribe lane region, then it is easy to access for testing, but it gets cut during dicing causing electrical shorts and deformation

Engineering Contradiction:

Improvetest pad accessibilityVSAvoidelectrical connection integrity

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The protective layer is formed over the test pad before the dicing process, preemptively protecting it from being cut. This preliminary protective action ensures that the test pad remains intact during subsequent manufacturing steps, resolving the contradiction between accessibility and integrity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective layer acts as an intermediary element between the test pad and the dicing blade. It provides a sacrificial barrier that prevents direct contact between the cutting tool and the test pad, thereby maintaining electrical connection integrity while still allowing test access through the protective layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the protective layer completely covers the scribe lane region, then it protects all structures, but it covers the test pad making it inaccessible

Engineering Contradiction:

Improvestructure protectionVSAvoidtest pad accessibility

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The protective layer is selectively formed to cover only specific regions - it protects the chip region and partially covers the scribe lane region while leaving the test pad exposed. This localized protection approach maintains both structure integrity and test accessibility by applying protection only where needed.

Inventive Principle:

Principle #3Local quality

3Productivity

If the test pad is cut during dicing, then separation is achieved, but electrical shorts and deformation occur

Engineering Contradiction:

Improvechip separation efficiencyVSAvoidtest pad integrity

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The protective layer serves as a mediator that allows the dicing process to proceed for chip separation while preventing the test pad from being cut. It enables productive separation without compromising manufacturing precision of the test pad structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective layer is selectively removed or designed to be present only in specific areas, extracting the protection function from the entire scribe lane and applying it only where necessary. This allows dicing to occur in the exposed scribe lane region while the test pad remains protected.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS11380595B2Semiconductor wafer, method for separating the semiconductor wafer, semiconductor chip, and semiconductor package including the semiconductor chip

Publication Date: 2022.07.05 SK HYNIX INC

AI summary

A semiconductor wafer includes a first chip region and a second chip region spaced apart from each other by a scribe lane region. The semiconductor wafer also includes a test pad disposed in the scribe lane region. The semiconductor wafer additionally includes a protective layer partially covering the first chip region, the second chip region, and the scribe lane region, wherein the protective layer covers a portion of the test pad adjacent to the first chip region and leaves a remaining portion of the first test pad exposed.