Wafer Test Pad Layout for Pre-Bond Defect Screening
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Solution Overview
Problem
Testing semiconductor wafers before bonding is challenging due to damage to contact pads from test probes, leading to poor wafer-to-wafer bonding and inefficient defect screening, especially in three-dimensional ICs where complete power delivery and ESD protection are lacking.
Innovation Solution
Incorporating test structures and pads in scribe lanes of semiconductor wafers, which are tested using probes before completing die formation, allowing for the formation of additional metal layers based on defect metrics to ensure wafer quality and prevent defective die production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wafers are tested prior to bonding to screen out defective dies, then defect detection capability is improved, but contact pads are damaged leading to poor wafer-to-wafer bonding
Solution Approach 1:
The wafer is divided into two distinct regions: scribe lanes containing test structures and die areas containing functional circuits. This segmentation allows testing to be performed on dedicated test structures without damaging the contact pads needed for bonding, as the test probes contact only the test pads in the scribe lanes rather than the bond pads in the die areas.
Solution Approach 2:
Dedicated test structures and test pads are introduced as intermediary elements that serve as substitutes for testing the actual functional circuits. These test structures act as mediators that absorb the testing activity, protecting the contact pads and functional circuits from damage while still enabling defect detection through the test metrics generated by the test structures.
2Reliability
If testing is performed after wafer bonding, then complete power delivery and ESD protection are available, but resource loss and production time increase significantly when defects are found
Solution Approach 1:
Testing is performed preliminarily, before wafer bonding and before completion of die formation. The test structures are evaluated at an intermediate stage when the wafer still has access to power delivery networks and ESD protection from previously formed layers, but before bonding occurs. This allows early defect detection to prevent wasting time and resources on bonding defective wafers.
Solution Approach 2:
The testing process generates metrics for each test structure that provide feedback on wafer quality. This feedback mechanism enables real-time assessment of whether the wafer meets predefined criteria for continued fabrication, allowing the process to be adjusted or stopped based on test results rather than discovering defects after bonding.
3Reliability
If complete die formation is completed before testing, then all power delivery and ESD protection circuits are available, but testing cannot be performed on wafers with incomplete circuits
Solution Approach 1:
The test structures are designed with local quality, meaning they are specifically configured to be self-contained and testable at intermediate fabrication stages. The test structures in the scribe lanes can be evaluated with the power delivery networks and ESD protection that are available at that stage, without requiring the complete set of circuits that would only be available after full die formation and bonding.
Data Source
AI summary
Disclosed herein are integrated circuit (IC) structures and methods for fabricating and testing such IC structures prior to dicing from a semiconductor wafer on which the IC structures are formed. In one example, a method for fabricating an IC structure includes contacting a first plurality of test pads of the IC structure with one or more test probes. The first plurality of test pads are disposed within or on a first dielectric layer within a scribe lane, i.e., a test region. A first metal layer is formed over the first plurality of test pads if a predefined test criteria is met as determined using information obtained through first plurality of test pads using the one or more test probes. The first metal layer is a layer formed in a die region of an IC die that is being fabricated in the wafer.