Wafer Test Sequence Optimization via Dynamic Machine Allocation
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Solution Overview
Problem
In semiconductor production, testing wafers according to a fixed test sequence on Runcard test sheets leads to inefficient use of testing machines and longer test times due to overlapping test item times for multiple wafers, resulting in wasted machine time and low wafer testing efficiency.
Innovation Solution
A method and device that optimize the test sequence for individual wafers by dividing them into units based on shared test items, determining a sequence that considers site priority, creation time, machine availability, and type, and idle time to efficiently allocate testing machines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If wafers are tested according to the fixed test sequence on Runcard test sheets, then the test process is simple to follow, but the testing machine utilization is low and test time is extended
Solution Approach 1:
The patent applies dynamics by transforming the fixed, static test sequence into a dynamic, optimized sequence. The system dynamically adjusts the test sequence based on real-time machine conditions (idle time, machine type, machine amount) and test item characteristics (site priority, creation time priority), allowing the test process to adapt and optimize itself rather than following a rigid predetermined path
Solution Approach 2:
The patent changes key parameters of the test process by introducing optimization variables such as site priority, creation time priority, machine idle time, machine type, and machine amount. These parameter changes enable the system to determine an optimized test sequence that maximizes machine utilization while maintaining test completeness
2Reliability
If one machine is turned on for one wafer, then the test sequence can be followed precisely, but machine resources are wasted and test time increases
Solution Approach 1:
The patent merges multiple test sequences and machine resources into a coordinated optimization framework. It combines test items from multiple wafers and allocates them across multiple machines simultaneously, merging previously separate test processes into an integrated system that reduces overall test time while maintaining sequence accuracy through the optimization algorithm
Solution Approach 2:
The patent ensures continuity of useful action by optimizing machine allocation to minimize idle time and maximize continuous testing operations. The system continuously assigns test items to available machines based on real-time conditions, ensuring that machines remain continuously productive rather than experiencing interruptions or idle periods
3Productivity
If multiple wafers share the same test step, then resource utilization improves, but the fixed sequence causes machine idle time and inefficiency
Solution Approach 1:
The patent segments the test process by dividing test items into independently optimizable units that can be allocated to different machines. It segments wafers into divided units based on their test item requirements, allowing flexible assignment to multiple machines simultaneously, thereby reducing machine idle time while maintaining high utilization
Data Source
AI summary
The present disclosure provides a method and a device for testing a wafer, an electronic device, and storage medium, wherein the method includes: obtaining plural test sheets; dividing the wafers to be tested in the plurality of test sheets according to individual test items in the plurality of test sheets, and determining the wafers to be tested corresponding to individual divided units; determining a test sequence of the test items to be performed on each wafer to be tested, based on a test sequence condition of the test items in individual test sheets and a test condition of a testing machine corresponding to individual divided units; and testing the wafer to be tested, according to the test sequence of the test items to be performed on any of the wafers to be tested.