Wafer Scribe-Line Test Structure for Accurate BLC Resistance Measurement
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Solution Overview
Problem
The resistance measurement methods for bit line contact (BLC) structures in DRAMs lack accuracy and fail to characterize the real resistance of the BLC structures in memory cells.
Innovation Solution
A test structure is formed in the scribe line of a wafer with a first and second active area connected by a contact structure that replicates the BLC structure in the die region, allowing for accurate resistance measurement by connecting a voltage measuring device and current input device to the conductive plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional resistance measurement methods are used, then measurement can be performed, but measurement precision is low and cannot characterize the real resistance of the BLC structure
Solution Approach 1:
The patent creates a copy of the BLC structure in the scribe line region that replicates the exact structure and fabrication process of the BLC in the die region. This copy includes the same contact hole, barrier layer, and conductive plug formation steps, allowing accurate resistance measurement without affecting the actual memory cell structures. The copied structure enables precise characterization while maintaining the integrity of production structures.
Solution Approach 2:
The patent separates the measurement function from the production function by placing test structures in the scribe line region, which is distinct from the die region containing memory cells. This segmentation allows independent optimization of measurement accuracy without compromising production yield or cell performance. The scribe line becomes a dedicated test area that can be accessed without disturbing functional structures.
2Measurement precision
If test structures are added to measure BLC resistance, then measurement capability is improved, but device complexity increases
Solution Approach 1:
The scribe line region serves multiple functions: it provides mechanical support for wafer handling, contains alignment marks for fabrication processes, and now houses test structures for electrical characterization. By utilizing this existing space for additional measurement functionality, the patent avoids adding separate dedicated test areas that would increase overall device complexity. The same fabrication processes that create BLC structures in die regions also create identical structures in scribe line test regions.
Solution Approach 2:
The patent combines the test structure fabrication with the production BLC structure fabrication by using identical process steps (contact hole etching, barrier layer deposition, conductive plug formation) in both die and scribe line regions. This merging of fabrication processes eliminates the need for separate test structure manufacturing steps, reducing overall process complexity while enabling accurate resistance measurement.
Data Source
AI summary
Embodiments of the present disclosure provide a test structure of a wafer and a method of manufacturing a test structure of a wafer, and relate to the technical field of semiconductors. The test structure of a wafer includes at least one test unit provided in a scribe line of the wafer, where the test unit includes a first active area and a second active area that are connected to each other; the first active area is provided with a first conductive plug, and the second active area is provided with a second conductive plug; and one of the first active area and the second active area is provided with a contact structure.