Wafer-Based Test Structure for Stacked Die Arrays
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Solution Overview
Problem
The widespread adoption of stacked die assemblies, such as Hybrid Memory Cube technology, is hindered by the laborious process of testing individual cubes, necessitating an automated solution for simultaneous testing of multiple stacked die assemblies to qualify them as 'known good cubes'.
Innovation Solution
A wafer-based test structure with an array of pockets and a redistribution layer is used to accommodate multiple die stacks, allowing for automated testing via a probe card or bond head, enabling simultaneous electrical characterization and verification of interconnect integrity, signal speed, and other parameters across multiple test sites.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If individual cube testing is performed, then testing accuracy is maintained, but testing throughput is limited
Solution Approach 1:
The test structure is segmented into multiple independent test sites (e.g., 64 test sites) arranged in an array on a single wafer. Each test site can independently accommodate and test one die stack, allowing parallel testing operations while maintaining the accuracy of individual cube testing through dedicated test circuits at each site.
Solution Approach 2:
Multiple test sites are merged onto a single wafer substrate, sharing common infrastructure such as the wafer base, encapsulant material, and overall structural support. This combining approach enables simultaneous testing of multiple die stacks while reducing the total number of separate test devices needed.
2Productivity
If multiple die stacks are tested simultaneously, then testing throughput increases, but test site alignment precision becomes more difficult
Solution Approach 1:
Each test site incorporates locally-optimized features including precisely positioned pockets with specific depth and diameter dimensions, locally-formed conductive contacts and traces, and site-specific alignment structures. These localized quality controls ensure that each test site maintains precise alignment and functional performance independent of other sites on the same wafer.
3Extent of automation
If automated testing is implemented, then labor requirements decrease, but device complexity increases
Solution Approach 1:
The test structure incorporates self-aligning features such as pockets that automatically position die stacks through mechanical interference fits, and conductive contacts that self-adjust to accommodate minor positioning variations. These self-service mechanisms reduce the complexity of automated positioning systems while maintaining high automation capability.
Data Source
AI summary
Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.