Wafer Test Trigger Signal Circuit for Semiconductor Memory
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Solution Overview
Problem
The existing semiconductor memory apparatus testing in a wafer state faces challenges in precisely determining the transition timing of address signals due to line characteristics, leading to difficulties in entering the required test mode, which increases test time and cost.
Innovation Solution
A wafer test trigger signal generating circuit that includes an enable timing control unit and a trigger signal generating unit to generate a test trigger signal, designating the decoding timing of test modes using address signals, thereby reducing signal skew and enabling the semiconductor memory apparatus to enter the required test mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If connection lines are used to connect the test apparatus to the semiconductor memory apparatus, then the test apparatus can control the transition timing of address signals, but the line characteristics cause signal skew that prevents precise determination of transition timing
Solution Approach 1:
The patent introduces a trigger signal as an intermediary between the test apparatus and the address decoding logic. This trigger signal is generated internally within the semiconductor memory apparatus and serves as a mediator that synchronizes the decoding operation without being affected by external line skew. The trigger signal is derived from the address signals themselves but is processed internally to eliminate the timing errors introduced by connection lines.
2Reliability
If the trigger signal is controlled by the test apparatus through connection lines, then the test mode can be entered, but the signal skew increases test time and cost
Solution Approach 1:
The semiconductor memory apparatus generates its own trigger signal internally using its own address signals and decoding logic. This self-service approach eliminates the need for the test apparatus to externally control the trigger timing, thereby removing the source of signal skew and reducing test time. The internal generation ensures that the trigger signal is always synchronized with the address signals regardless of external line characteristics.
3Ease of operation
If multiple connection lines are used between the test apparatus and the semiconductor memory apparatus, then the test apparatus can control address signal timing, but the number of connection lines increases device complexity
Solution Approach 1:
The patent extracts the trigger signal generation function from the test apparatus and relocates it to the semiconductor memory apparatus itself. This extraction eliminates the need for additional connection lines between the test apparatus and the memory apparatus for trigger control. The test apparatus only needs to provide the basic address signals, and the memory apparatus internally generates the trigger signal from these addresses, thereby reducing the number of required connection lines and simplifying the overall system complexity.
Data Source
AI summary
A wafer test trigger signal generating circuit of a semiconductor memory apparatus includes an enable timing control unit configured to generate an enable signal by using a plurality of address signals, and a trigger signal generating unit configured to generate a test trigger signal, which designates a decoding timing of a test mode defined by the plurality of address signals, in response to the enable signal.