Wafer Test Unit Loop-Back Sections for Signal Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing test systems face challenges in accurately performing loop-back tests on semiconductor circuits due to signal degradation caused by lengthy transmission paths and the difficulty in integrating noise generation circuits on performance boards, especially when testing multiple circuits on a wafer simultaneously.
Innovation Solution
A test wafer unit with semiconductor material, incorporating loop-back sections that directly exchange signals with each circuit under test, reducing transmission paths and enabling accurate loop-back testing without the need for external drivers or noise generation circuits, and a control apparatus to manage these tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the signal is fed back in the main body of the test apparatus, then the signal can be looped back to the circuit under test, but the transmission path is lengthened causing signal degradation
Solution Approach 1:
The test system is divided into two functional parts: the main body for controlling multiple circuits and the performance board for handling individual circuit testing. Each circuit under test is assigned a dedicated loop-back path on the performance board, allowing signal feedback without passing through the main body, thus shortening the transmission path while maintaining the ability to test multiple circuits en bloc.
Solution Approach 2:
The performance board acts as an intermediary between the main body and the circuits under test. It receives control signals from the main body and provides dedicated loop-back paths for each circuit, serving as a mediator that enables short transmission paths while maintaining system-wide control capability.
2Length of moving object
If a loop-back path is provided for each circuit under test on the performance board, then the transmission path is shortened, but the device complexity increases due to the need for multiple noise generation circuits
Solution Approach 1:
The performance board is designed with universal functionality to handle multiple circuits simultaneously. Each circuit under test shares the same performance board infrastructure, and the board can perform loop-back testing for multiple circuits en bloc without requiring separate noise generation circuits for each path, thus reducing overall device complexity while maintaining short transmission paths.
Solution Approach 2:
Multiple loop-back paths are merged onto a single performance board substrate. Instead of providing separate noise generation circuits for each loop-back path, the system combines all loop-back functions on one board, allowing parallel testing of multiple circuits with shared resources, thereby reducing the total number of components required.
3Adaptability or versatility
If noise generation circuits are added to each loop-back path, then noise can be added to the signal, but it is difficult to dispose noise generation circuits on the performance board
Solution Approach 1:
The performance board integrates multiple functions including signal routing, loop-back paths, and noise generation capabilities into a single substrate. By merging these functions, the system achieves adaptability for signal processing while maintaining ease of manufacture, as all components are disposed on one board rather than requiring separate assemblies for each loop-back path.
Solution Approach 2:
The performance board is designed as a universal platform that can handle multiple circuits and provide various signal processing functions including noise generation. This multi-functional design allows the board to adapt to different testing requirements while maintaining a standardized, manufacturable structure that doesn't require custom noise generation circuits for each individual path.
Data Source
AI summary
Provided is a test wafer unit that tests a plurality of circuits under test formed on a wafer under test. The test wafer unit comprises a test wafer that is formed of a semiconductor material and exchanges signals with each of the circuits under test, and a plurality of loop-back sections that are provided in the test wafer to correspond to the plurality of circuits under test and that each supply the corresponding circuit under test with a loop-back signal corresponding to a signal received from the corresponding circuit under test.