Wafer Testing Without Direct Probing Using Mesh Signal Busses
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Solution Overview
Problem
Conventional direct probing technologies are inadequate for testing small integrated circuits (chiplets) due to their small connection points and pitches, leading to limited test coverage and potential damage during probing, which increases manufacturing costs and requires scrapping of defective chiplets.
Innovation Solution
The implementation of a test integrated circuit die that uses power and signal busses to connect with adjacent product IC dies, allowing for in-wafer testing through a mesh structure and routing circuits that enable flexible test paths and rerouting around defective dies, facilitating efficient and non-destructive testing before wafer scribing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional direct probing technology is used to test small integrated circuits (chiplets), then testing can be performed, but the small connection points and pitches lead to limited test coverage and potential damage during probing
Solution Approach 1:
The patent introduces an intermediary test die with a master test circuit that interfaces between the external tester and the product IC dies. This master test die acts as a mediator that receives test signals from the tester and distributes them to multiple product IC dies through signal busses, enabling comprehensive testing without direct probing of each small connection point. The intermediary structure protects the fragile chiplet connections while maintaining full test coverage.
Solution Approach 2:
The testing system is segmented into separate functional components: a master test die containing the test circuitry, product IC dies containing the circuits under test, and signal busses for interconnection. This segmentation allows the test functions to be concentrated in larger, more robust structures while the product IC dies can remain small, resolving the contradiction between test coverage and connection point size.
2Reliability
If conventional direct probing is used on small pitch chiplets, then testing can occur, but manufacturing costs increase and defective chiplets must be scrapped
Solution Approach 1:
The patent implements preliminary testing of product IC dies at the wafer level before final packaging and assembly. By testing chiplets while they are still on the wafer substrate, defects are identified early in the manufacturing process, allowing defective dies to be isolated and removed without scrapping entire assemblies. This preliminary action significantly reduces manufacturing costs by enabling selective elimination of only the defective units.
Solution Approach 2:
The system enables self-testing capabilities where product IC dies can be tested through their own integrated test circuits and signal busses without requiring external probing equipment for each individual die. The master test die provides automated test signal distribution and result collection, reducing the need for expensive manual or automated probing operations.
3Area of moving object
If small pitch interconnect technologies are used for chiplets, then integration density increases, but conventional probing cannot adequately test the connection points
Solution Approach 1:
The patent transitions from direct probing (one-dimensional contact) to a mesh-like signal distribution network operating in multiple dimensions. Signal busses are routed through the wafer substrate in horizontal and vertical directions, creating a two-dimensional test access network that can reach all product IC dies without requiring direct vertical probing of each small connection point. This dimensional transformation enables testing of high-density interconnects that would be inaccessible to conventional probing.
Solution Approach 2:
The signal busses and master test die are designed to provide universal testing capability across multiple product IC dies with different functions and configurations. The same test infrastructure can test various types of chiplets (CPU, GPU, memory, etc.) by routing appropriate test signals through the mesh network, making the testing system universally applicable to diverse small pitch interconnect technologies.
Data Source
AI summary
The invention pertains to in-wafer testing of integrated circuits. In particular, it pertains to apparatuses and methods for testing small integrated circuits that have pad sizes and pitches that are too small for using conventional wafer probing technology.