Wafer Testing System Parallel Program Execution
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Solution Overview
Problem
Traditional wafer testing methods are inefficient as they can only execute one testing program at a time, leading to unnecessary parameter measurement and prolonged testing times, which damages probe card pins and results in incorrect test results.
Innovation Solution
A wafer testing system that assigns multiple testing programs to multiple wafers, with each program including specific algorithms and conditions, allowing the processor to execute these programs and conditions to measure wafer parameters efficiently, using a test head and probe card to create an electrical path for testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one testing program is executed to test a whole batch of wafers, then all wafers can be tested, but plenty of time is spent on measuring unnecessary parameters or testing unnecessary wafers, resulting in low efficiency
Solution Approach 1:
The patent divides the batch of wafers into multiple groups, with each group assigned a specific testing program. The processor determines which testing program to execute for each wafer based on its characteristics, allowing parallel execution of multiple testing programs simultaneously. This segmentation eliminates the need to execute one program sequentially for all wafers, significantly improving testing efficiency and reducing total testing time.
2Reliability
If one testing program is executed to test a whole batch of wafers, then all wafers can be tested, but long testing time damages the pins of probe card, resulting in incorrect test results
Solution Approach 1:
The patent segments the testing process into multiple programs executed in parallel on different wafer groups. By distributing the testing workload across multiple programs rather than running one program for the entire batch, the duration each probe card pin remains engaged is reduced. This minimizes mechanical stress and damage to the pins, maintaining their integrity and ensuring accurate test results.
Solution Approach 2:
The system dynamically assigns different testing programs to different groups of wafers based on processor determination. This dynamic approach allows the testing system to adapt to different wafer characteristics and optimize the testing sequence, reducing the overall engagement time of probe card pins and minimizing cumulative damage throughout the testing process.
3Productivity
If one testing program is executed to test a whole batch of wafers, then all wafers can be tested, but plenty of time is spent on measuring unnecessary parameters, resulting in low efficiency
Solution Approach 1:
The patent segments the batch of wafers into multiple groups, each tested by a dedicated testing program. Each program is tailored to measure only the necessary parameters for its assigned wafer group. This eliminates the waste of energy that occurs when a single program measures all parameters for all wafers, including unnecessary measurements. The segmentation ensures that energy resources are focused only on relevant measurements for each group.
Data Source
AI summary
The present disclosure provides a wafer testing method, including: assigning multiple testing programs to multiple wafers, wherein each of the testing programs includes testing algorithms configured to measure parameters of the wafers; setting multiple sets of testing conditions for the testing programs; and testing at least one of the wafers by executing a corresponding one of the testing programs according to a corresponding one of the testing conditions.