Wafer-Scale Thermal Interposer With Zoned Heating and EMI Shielding
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Solution Overview
Problem
Conventional environmental testing of integrated circuits is limited by the need for large environmental chambers, which degrade testing accuracy, limit testing rates, and require complex mechanisms for inserting and removing DUTs, while chamber-less systems face difficulties in cooling integrated circuits effectively, especially at a wafer level.
Innovation Solution
A wafer scale active thermal interposer device with independently controllable thermal zones and an EMI shield layer, capable of heating and cooling different portions of a wafer to precise temperatures, compatible with existing testing systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If environmental chambers are used for testing integrated circuits, then environmental testing can be performed, but testing accuracy is degraded and testing rate is limited
Solution Approach 1:
The patent extracts the thermal control function from the environmental chamber and integrates it directly into the interposer device. The interposer includes heating elements and cooling structures that can independently control temperatures of multiple dice without requiring a large environmental chamber, thereby improving testing accuracy and simplifying the testing system.
Solution Approach 2:
The interposer acts as an intermediary between the test system and the dice. It provides direct thermal control to each die through integrated heating and cooling structures, eliminating the need for complex environmental chamber mechanisms while enabling precise temperature control for accurate testing.
2Productivity
If environmental chambers are used for testing integrated circuits, then environmental testing can be performed, but testing rate is limited
Solution Approach 1:
The patent removes the large environmental chamber from the testing system and replaces it with a compact interposer device that provides direct thermal control. This extraction eliminates the volume constraints and mass of mounting structures, enabling faster testing rates.
Solution Approach 2:
The patent replaces the mechanical environmental chamber system with an integrated thermal control system embedded in the interposer. This substitution eliminates the need for large volumes of air and heavy mounting structures, significantly improving testing throughput and rate.
3Productivity
If chamber-less test systems are used to heat and cool DUT directly, then many limitations of chamber-based testing are overcome, but cooling integrated circuits under test becomes difficult
Solution Approach 1:
The patent segments the thermal control into independent heating and cooling systems within the interposer. The heating elements can be selectively activated for specific dice, while the cooling structure provides active cooling capability, overcoming the limitation of chamber-less systems and enabling effective temperature control for high throughput testing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise and efficient environmental testing of integrated circuits at a wafer level, increasing manufacturing throughput by identifying defective dies early and reducing testing time.
Implementation Method 1
a heating layer defining a plurality of independently controllable thermal zones... electrical power is configured to be selectively applied to one or more of the plurality of independently controllable thermal zones
Implementation Method 2
an electromagnetic interference (EMI) shield layer defining the top surface and disposed to shield the top surface from EMI from the heating layer
Data Source
AI summary
A system for testing circuits of an integrated circuit semiconductor wafer includes a thermal interposer (TI) device for use in testing circuits of a semiconductor device. The TI device includes a top surface configured to receive the semiconductor device, a heating layer defining a plurality of independently controllable thermal zones configured to maintain or change temperatures of the top surface during the testing, a power input configured to receive electrical power and wherein the electrical power is configured to be selectively applied to one or more of the plurality of independently controllable thermal zones, and an electromagnetic interference (EMI) shield layer defining the top surface and disposed to shield the top surface from EMI from the heating layer.