Wafer Thinning via Notch-Defined CMP for TSV Exposure
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Solution Overview
Problem
Total thickness variation (TTV) post backside via reveal (BVR) process in semiconductor wafer thinning leads to non-uniform exposure of blind conductive through-silicon vias (TSVs), causing electrical shorts or discontinuity due to varying etch rates of mold compound and semiconductor material.
Innovation Solution
A method involving backgrinding, edge trimming, and chemical mechanical polishing (CMP) to uniformly expose conductive vias, where a notch is created in the encapsulant and substrate to eliminate the encapsulant/base material interface at the CMP level, ensuring coplanarity and reducing TTV issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMP process is used to expose conductive TSVs, then electrical connection is achieved, but non-uniform etching rate causes total thickness variation and reliability issues
Solution Approach 1:
The patent divides the wafer into two distinct regions: a first region with encapsulant removed to expose TSVs, and a second region with encapsulant retained. This segmentation allows different processing conditions to be applied to different areas, enabling uniform TSV exposure in the first region while preserving the structural integrity and electrical continuity provided by the encapsulant in the second region.
Solution Approach 2:
The patent applies different treatments to different regions of the wafer. The first region undergoes encapsulant removal and CMP processing to expose TSVs for electrical connection, while the second region maintains its encapsulant for structural support and uniform thickness. This local differentiation resolves the contradiction by providing both electrical continuity and thickness uniformity in appropriate areas.
2Reliability
If encapsulant is removed to expose TSVs, then electrical connection is improved, but structural support and thickness uniformity are compromised
Solution Approach 1:
The patent segments the wafer structure into a first region where encapsulant is removed for electrical connection, and a second region where encapsulant is retained for structural support. This spatial segmentation allows both electrical and mechanical requirements to be satisfied simultaneously in different areas of the same device.
Solution Approach 2:
The patent selectively extracts (removes) the encapsulant only from the first region where TSV exposure is needed for electrical connection, while leaving the encapsulant intact in the second region to maintain structural support and thickness uniformity. This selective extraction resolves the contradiction by removing material only where necessary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces TTV, prevents over- or under-etching, and minimizes defects by uniformly exposing conductive TSVs, ensuring consistent electrical continuity and reliability.
Implementation Method 1
The CMP process gradually removes semiconductor material from back surface 16 to reveal or expose the TSVs without damaging other portions of semiconductor wafer 12
Implementation Method 2
The BVR is accomplished by chemical mechanical polishing (CMP) of back surface 16 using chemical slurries in combination with mechanical, physical-contact etching
Data Source
AI summary
A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.