Semiconductor Wafer Thinning via Segmented Backside Grinding
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Solution Overview
Problem
The TAIKO process for thinning semiconductor wafers often results in cracking due to the rough ground surface left by coarse grinding, which becomes more significant as the wafer thickness decreases, as the inner region is ground more than the outer periphery during finish grinding.
Innovation Solution
A method involving three grinding steps: first, an annular groove is formed on the back surface with a finer grindstone, followed by rough grinding of the inner projecting portion with a coarser grindstone, and finally, finish grinding of the recessed portion with an even finer grindstone to create a smooth surface, ensuring the internal surface is only made by the first and third grindstones, reducing the risk of cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If finish grinding is performed with a fine grindstone on the inner region, then the flatness and surface quality are improved, but a rough ground surface remains around the outer periphery which causes cracking
Solution Approach 1:
The patent divides the wafer surface into two distinct regions: a first ground region (outer periphery) ground by a coarse grindstone and a second ground region (inner region) ground by a fine grindstone. This segmentation allows each region to be treated differently, with the first region providing structural support and the second region providing the required flatness, thereby preventing cracking while achieving manufacturing precision.
Solution Approach 2:
The patent applies different grinding qualities to different parts of the wafer. The outer peripheral region is ground with a coarse grindstone to maintain mechanical strength and avoid cracking, while the inner region is ground with a fine grindstone to achieve the required flatness and surface quality. This local differentiation of grinding quality resolves the contradiction between preventing cracks and achieving precision.
2Productivity
If the semiconductor wafer is thinned, then the device performance is improved, but the mechanical strength decreases and cracking becomes more likely
Solution Approach 1:
The patent creates a thickness gradient across the wafer by grinding only the inner region (second ground region) while leaving the outer peripheral region (first ground region) thicker. This local differentiation in thickness maintains mechanical strength at the edges while achieving the required thinness in the center for device performance, thereby resolving the contradiction between thinning and strength maintenance.
3Productivity
If rough grinding is performed with a coarse grindstone, then processing efficiency is improved, but the ground surface becomes rough which causes cracking
Solution Approach 1:
The patent segments the grinding process into two distinct operations: rough grinding of the outer peripheral region with a coarse grindstone for efficiency, and finish grinding of the inner region with a fine grindstone for surface quality. This segmentation allows each grinding operation to be optimized for its specific purpose without compromising the other.
Solution Approach 2:
The patent applies different surface qualities to different regions: the outer peripheral region receives a rougher finish from the coarse grindstone which is acceptable for that area, while the inner region receives a fine finish from the fine grindstone where surface quality is critical. This local differentiation resolves the contradiction between processing efficiency and surface precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses cracking in thinned semiconductor wafers and facilitates handling by ensuring the internal surface of the recessed portion is smooth, reducing the likelihood of cracking and improving processing efficiency.
Implementation Method 1
grinding an outer edge portion on a back surface of a semiconductor wafer with a first grindstone or blade to thereby form an annular groove
Implementation Method 2
grinding a projecting portion on an inner side of the groove with a second grindstone to thereby form a recessed portion integrally with the groove on the back surface of the semiconductor wafer
Implementation Method 3
grinding a bottom surface of the recessed portion including a ground surface made by the second grindstone with a third grindstone
Data Source
AI summary
According to one embodiment, a substrate processing method is disclosed. The above method includes: grinding an outer edge portion on a back surface of a semiconductor wafer with a semiconductor element formed on its front surface with a first grindstone or blade to thereby form an annular groove; grinding a projecting portion on an inner side of the groove with a second grindstone to thereby form a recessed portion integrally with the groove on the back surface of the semiconductor wafer; and grinding a bottom surface of the recessed portion including a ground surface made by the second grindstone with a third grindstone.