Wafer Topography and Design Data Integration for Hotspot Detection
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Solution Overview
Problem
Current semiconductor manufacturing processes lack effective methods for detecting design defects, particularly hotspots, which can cause device failure due to their reliance on traditional inspection methods that do not consider wafer or chip topography, as device dimensions shrink and design rules approach performance limits.
Innovation Solution
A method involving the reception of integrated circuit design data, measurement of wafer topography, calculation of a scanner moving average to create a defocus map, and determination of hotspot design defects, which considers the wafer's topography and design data to identify and potentially compensate for defects before photolithography processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional inspection methods are used to detect defects, then the inspection process is simple, but the detection sensitivity is insufficient and cannot identify hotspot defects
Solution Approach 1:
The patent combines multiple data sources including wafer topography data, design data, and scanner defocus maps into a unified inspection system. This merging of data types enables the detection of hotspot defects that traditional single-method inspection cannot identify, directly improving detection sensitivity while managing complexity through integrated processing.
Solution Approach 2:
The patent introduces a new dimension of analysis by incorporating wafer topography (z-height information) alongside traditional two-dimensional design data. This third dimension enables the identification of hotspot defects related to focus variations across the wafer surface, significantly enhancing detection capability beyond conventional planar inspection methods.
2Productivity
If design rules are shrunk to increase device density, then productivity increases, but defect impact on device performance increases
Solution Approach 1:
The patent performs preliminary detection of hotspot defects before photolithography processing by analyzing wafer topography and calculating scanner defocus maps. This advance identification allows for potential compensation or process adjustment before manufacturing, preventing reliability issues that would otherwise arise from shrinking design rules and increasing device density.
Solution Approach 2:
The system provides feedback by generating hotspot defect maps that indicate locations and severity of potential defects. This feedback mechanism enables process engineers to adjust manufacturing parameters or compensate for topography variations, maintaining device performance reliability even as design rules shrink and device density increases.
3Measurement precision
If wafer topography is not considered in inspection, then the inspection process is faster, but hotspot defects related to topography cannot be detected
Solution Approach 1:
The patent performs preliminary measurement of wafer topography using an inspection tool before the main defect detection analysis. This advance topography characterization enables subsequent rapid identification of hotspot defects by comparing design data against pre-acquired topography information, achieving high detection accuracy while minimizing inspection time through efficient data utilization.
Data Source
AI summary
In one embodiment, a method for detecting design defects is provided. The method includes receiving design data of an integrated circuit (IC) on a wafer, measuring wafer topography across the wafer to obtain topography data, calculating a scanner moving average from the topography data and the design data to provide a scanner defocus map across the wafer, and determining a hotspot design defect from the scanner defocus map. A computer readable storage medium, and a system for detecting design defects are also provided.