Semiconductor Wafer Traceability Using Defect Maps and Metal Film Images
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Solution Overview
Problem
Existing methods for identifying defects in semiconductor devices after manufacturing are costly and lack accuracy, making it difficult to trace the cause of defects and provide timely feedback to the manufacturing process.
Innovation Solution
Assign a wafer identification number to a silicon carbide wafer, partition it into chip areas, inspect for crystal defects, store position information, form a metal film, acquire surface morphology images, and link this information to identify defects in semiconductor devices even after packaging, without assigning individual identification marks to each chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identification marks are assigned to all semiconductor chips, then traceability is enabled, but manufacturing costs increase
Solution Approach 1:
The patent segments the traceability approach by dividing the wafer into multiple chip areas with unique position information. Instead of marking each individual chip, the system creates a wafer map that segments and records the location of each chip area, enabling identification through positional data rather than physical marks on every chip.
Solution Approach 2:
The patent transitions from one-dimensional individual chip marking to a two-dimensional wafer-level mapping system. By creating a wafer map that records position information of multiple chip areas in a matrix arrangement, the system enables traceability through spatial coordinates rather than requiring marks on each chip surface.
2Ease of manufacture
If no identification marks are assigned to semiconductor chips, then manufacturing costs are reduced, but traceability accuracy deteriorates
Solution Approach 1:
The patent performs preliminary actions by capturing surface morphology images of metal films and recording position information of chip areas before the chips are diced and packaged. This advance documentation creates a reference database that enables later identification without requiring physical marks on the final chips.
Solution Approach 2:
The patent creates copies of surface morphology images and position information that serve as identification references. Instead of marking chips, the system captures and stores images of metal film surfaces with their positional data, using these copies for later matching and identification purposes.
3Reliability
If surface morphology images of metal films are captured and stored, then defect cause identification is enabled, but data processing complexity increases
Solution Approach 1:
The patent introduces position information of chip areas as an intermediary that links surface morphology images to specific locations on the wafer. This intermediary data structure enables the matching process by providing coordinates that connect images to their original positions, simplifying the overall identification system.
Solution Approach 2:
The patent implements feedback by matching captured surface morphology images with images of defective chips to identify defect causes. The system uses the stored position information and reference images to provide feedback about the origin and cause of defects, enabling corrective actions in the manufacturing process.
Data Source
AI summary
A technique that not only suppresses cost increase but also enables traceability of semiconductor devices with high accuracy is demanded. By mapping positions of crystal defects, position information of the crystal defects on a wafer map is stored in a memory device. In each of a plurality of chip areas, a metal film is formed in a wiring layer located above a semiconductor element. In each of the plurality of chip areas, a surface morphology image of a specific area of the metal film is acquired. The position information of the crystal defects on the wafer map, a wafer identification number, position information of the plurality of chip areas, position information of the specific area in the chip area, and the surface morphology image for each of the plurality of chip areas are linked and stored in a memory device.