Wafer-Level Transducer Integration for Wire-Bonded Multilayer Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing techniques for embedding active elements in integrated circuits during wafer level fabrication are not suitable for multilayered stacking, prohibiting the use of wire bonding techniques for interconnection between wafers.
Innovation Solution
The integration of active elements is achieved through a wafer level integration scheme where a cap wafer with transducer elements is bonded to a base wafer structure via an intermediating wafer, allowing for wire bonding and enabling a multilayered structure with improved heat dispersion and simplified fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional capping techniques are used to embed active elements in integrated circuits, then the active elements are enclosed and protected, but wire bonding techniques cannot be used to interconnect between wafers
Solution Approach 1:
The patent divides the integrated circuit structure into separate base wafer and cap wafer components that are processed independently and then assembled. This segmentation allows wire bonding to be performed on the base wafer before cap attachment, enabling interconnection while maintaining active element protection through the cap structure.
Solution Approach 2:
The patent performs wire bonding operations on the base wafer before attaching the cap wafer. This preliminary action enables electrical interconnections to be established while the active elements are still accessible, after which the cap is attached to protect the active elements without compromising the previously established connections.
2Productivity
If multilayered stacking of wafers with active elements is implemented, then integration density is improved, but traditional capping techniques prohibit wire bonding interconnections
Solution Approach 1:
The multilayered structure is segmented into base wafer and cap wafer that can be processed separately. Wire bonding is performed on the base wafer in the first layer before cap attachment, enabling interconnections in the stacked configuration without compromising integration density.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacked architecture by implementing multilayered wafer configuration. This dimensional change increases integration density while wire bonding is performed in the lateral dimension on accessible surfaces before cap attachment.
3Reliability
If active elements are enclosed under capping elements during wafer level fabrication, then element protection is achieved, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into independent stages: base wafer processing with wire bonding, then cap wafer attachment. This segmentation simplifies each individual process step while achieving the combined goals of element protection and interconnection, reducing overall fabrication complexity compared to attempting all operations simultaneously.
Solution Approach 2:
Wire bonding and other preliminary operations are performed on the base wafer before cap attachment. This preliminary action approach simplifies the fabrication process by executing complex operations when elements are accessible, then protecting them with cap attachment rather than attempting to perform all operations through complex integrated processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method facilitates the construction of integrated circuits with embedded transducer elements, enabling efficient electrical coupling and improved heat dissipation, and allows for simplified planar tile architectures.
Implementation Method 1
The wafer of active elements is bonded to an intermediating wafer configured to provide connectivity between the wafer of active elements and the plurality of interfacing dies
Implementation Method 2
The cap wafer structure is then attached and electrically connected (e.g., by a wafer-to-wafer bonding process) to the base wafer structure
Implementation Method 3
The interfacing dies are configured to interface between the active elements and the interposer wafer in a wafer-level-packaging process, whereby a base wafer structure is obtained utilizing wire bonding
Data Source
AI summary
An integrated circuit assembly and a method for fabricating the same are disclosed. The integrated circuit assembly includes: a base structure including an interposer board and a plurality of interfacing dies electrically coupled to said interposer board; a cap structure including an intermediating board and a panel of active elements having a plurality of active elements electrically coupled to the intermediating board. The cap structure is attached to the base structure such that the active elements are electrically coupled to the interfacing dies. Also disclosed are a tile including a backend circuit board configured to attach to the plurality of integrated circuits and provide electrical connectivity thereto the plurality of integrated circuits, and a method of fabricating the same, as well as an array of the plurality of such tile in cascade connection.