Wafer Transfer Layout With Bypass Paths for Higher Throughput
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Solution Overview
Problem
Current semiconductor wafer processing systems face inefficiencies in transferring wafers between processing modules, leading to increased complexity and reduced throughput due to the need for multiple transfer mechanisms and paths, which complicates the processing and inspection processes.
Innovation Solution
A substrate processing apparatus with a carrier block, first and second processing blocks, and a relay block, utilizing shared main transfer mechanisms and bypass transfer mechanisms to streamline wafer transfer paths, reducing the number of transfer steps and enhancing throughput by allowing direct transfer between processing blocks without passing through unnecessary modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple transfer mechanisms are used to transfer wafers between processing modules, then wafer transfer capability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple transfer mechanisms into a unified transfer system that serves multiple processing blocks. The transfer mechanism is configured to transfer wafers between different processing blocks and modules through a shared pathway, reducing the total number of separate transfer mechanisms needed while maintaining comprehensive wafer transfer capability across the semiconductor processing apparatus.
Solution Approach 2:
The transfer mechanism is designed with multi-functionality to perform various transfer operations including transferring wafers between processing blocks, between processing modules within blocks, and bypassing certain modules when needed. This universal transfer capability eliminates the need for dedicated transfer mechanisms for each specific transfer path, thereby reducing overall system complexity.
2Adaptability or versatility
If wafers are transferred through multiple processing blocks including relay blocks, then processing versatility is improved, but processing time increases
Solution Approach 1:
The patent implements dynamic transfer paths that can be adjusted based on processing requirements. The transfer mechanism can dynamically select whether to route wafers through relay blocks for additional processing or to bypass relay blocks when direct transfer is sufficient. This dynamic adaptability allows the system to optimize transfer time for each wafer based on the specific processing needs, reducing unnecessary transfer time while maintaining processing versatility.
Solution Approach 2:
The transfer mechanism is configured to enable skipping of certain processing blocks or modules when their processing is not required for a particular wafer. This allows wafers to be transferred directly between processing blocks without stopping at intermediate relay blocks, significantly reducing transfer time for wafers that do not require additional processing at those intermediate locations.
3Productivity
If bypass transfer mechanisms are added to reduce transfer steps, then productivity is improved, but device complexity increases
Solution Approach 1:
The bypass transfer capability is merged into the existing unified transfer mechanism rather than being implemented as separate bypass mechanisms. The transfer mechanism is configured with multiple selectable paths including direct paths that bypass relay blocks and processing modules. This integration allows the bypass functionality to be achieved without adding significant structural complexity, as the same transfer mechanism handles both normal and bypass transfer operations.
Data Source
AI summary
A substrate processing apparatus includes; a carrier block; a first processing block including first lower and upper processing blocks to deliver a substrate to and from the carrier block; a second processing block including second lower and upper processing blocks provided adjacent to the first lower and upper processing blocks; a relay block including a lifting and transferring mechanism that delivers the substrate between the second lower and upper processing blocks; a controller that controls an operation of each main transfer mechanism such that one of upper and lower processing blocks forms an outward path through which the substrate is transferred from the carrier block to the relay block and the other forms a return path through which the substrate is transferred from the relay block to the carrier block; and a bypass transfer mechanism provided for each of the first and second processing blocks.