Wafer Transfer Timing Coordination in Substrate Processing
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Solution Overview
Problem
Existing substrate processing apparatuses face inefficiencies in transferring wafers between processing chambers due to varying processing times, leading to unnecessary idle time and reduced throughput, as they primarily focus on the shortest remaining processing time without considering the time required for each chamber, causing wafers to wait excessively in standby.
Innovation Solution
A substrate processing apparatus and method that coordinates wafer transfers based on the specific processing times of each chamber, optimizing transfer timing to minimize wait times and maximize throughput by determining optimal transfer ratios and frequencies for each processing chamber.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafers are transferred based on the shortest remaining processing time, then the operation rate of processing chambers is improved, but wafers experience excessive wait times in standby and unnecessary idle time occurs
Solution Approach 1:
The patent changes the transfer timing parameters from being based solely on shortest remaining processing time to being based on coordinated transfer timing that considers processing times of multiple chambers. The control unit calculates optimal transfer timing for each wafer to minimize both chamber idle time and wafer wait time, transforming the transfer strategy from a single-chamber focus to a multi-chamber coordinated approach.
2Productivity
If wafers are continuously transferred to maintain maximum throughput, then processing throughput is improved, but processing chambers experience unnecessary idle time due to mismatched transfer timing
Solution Approach 1:
The control unit continuously monitors the processing times of multiple processing chambers and uses this feedback information to dynamically adjust wafer transfer timing. By receiving real-time data on chamber processing status and calculating optimal transfer moments, the system ensures wafers are transferred precisely when chambers become available, eliminating idle time while maintaining continuous throughput.
Data Source
AI summary
In a substrate processing apparatus according to the present invention, wafer transfer timing with which wafers are to be transferred to individual processing chambers from a cassette container is determined in correspondence to each processing chamber, based upon the lengths of time required to process a single wafer in the processing chambers. Then, wafers are transferred from the cassette container in conformance to the transfer timing thus determined. By setting the wafer transfer timing with which wafers are transferred from the cassette container in coordination with the lengths of processing time at the individual processing chambers, the operation rates in the processing chambers are improved and ultimately, the throughput of the apparatus is improved.