Single Wafer Multi-Level Transistor Fabrication
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Solution Overview
Problem
Existing methods for fabricating sample wafers with different transistor characteristics require multiple wafers and numerous diffusion steps, leading to high costs and long testing times due to variations between substrates and the need for multiple wafers to achieve desired transistor levels.
Innovation Solution
A method that forms channel regions with different impurity concentrations on a single wafer using multiple resist patterns and exposure shots, allowing for the creation of transistors with various threshold characteristics without requiring multiple wafers, thereby reducing variations and the number of diffusion steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple wafers are used to form transistors with different characteristics, then transistor level variation can be controlled, but substrate variations between wafers increase and manufacturing complexity increases
Solution Approach 1:
The patent combines multiple transistor levels that previously required separate wafers into a single wafer. By forming different channel regions (first through fourth channel regions) with different impurity concentrations on one wafer, the invention merges what were previously four separate wafers into one, reducing substrate variations and simplifying the manufacturing process while maintaining precise control over transistor characteristics.
Solution Approach 2:
The patent applies local quality by creating spatially varying impurity concentrations within different regions of the same wafer. Each channel region (first, second, third, fourth) is doped with different impurity concentrations to achieve different transistor characteristics (Tr1-Tr4), allowing each local region to have the specific properties needed for different transistor levels while maintaining overall process consistency across the entire wafer.
2Adaptability or versatility
If four separate wafers are prepared for different transistor levels, then each transistor characteristic can be optimized, but the number of diffusion steps increases and costs increase
Solution Approach 1:
The invention merges four separate diffusion processes that were previously applied to four different wafers into a single integrated process on one wafer. By forming all four channel regions with different impurity concentrations in sequence on the same substrate, the patent reduces the total number of diffusion steps from four separate wafer processes to one unified process, thereby reducing manufacturing complexity and costs while maintaining the ability to produce transistors with four different characteristic levels.
Solution Approach 2:
The patent segments the wafer into four distinct regions (first through fourth channel regions), each with different impurity concentrations tailored for specific transistor characteristics. This segmentation allows each region to be independently optimized for different transistor levels (Tr1-Tr4) while being processed together in a unified manufacturing flow, achieving both customization and process efficiency.
3Reliability
If multiple wafers are used for different transistor levels, then desired leakage current and switching characteristics can be achieved, but testing time increases due to evaluating multiple sample wafers
Solution Approach 1:
The patent merges four separate test evaluations that were previously required for four different wafers into a single test process. By incorporating all four transistor levels (Tr1-Tr4) on one wafer, the invention allows testing equipment to evaluate all transistor characteristics simultaneously on a single substrate, reducing the total testing time and equipment usage from evaluating four separate wafers to evaluating one comprehensive wafer, while maintaining full coverage of required performance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of a sample wafer with multiple transistor levels on a single wafer, reducing costs and eliminating substrate variations, while allowing for efficient estimation of transistor characteristics and reduced testing time.
Implementation Method 1
implants a P-type ion, for example, into a formed resist pattern (S103) and removes the resist (S104). After that, the process coats another resist (S105), performs exposure and development (S106), then implants an N-type ion (S107)
Data Source
AI summary
A wafer fabrication method includes a first step of forming a plurality of first channel regions in a first region on a surface of a water, a second step of forming a plurality of second channel regions having an impurity concentration different from an impurity concentration of the first channel regions, a third step of forming a plurality of third channel regions in a third region on the surface of the water, and a fourth step of forming a plurality of fourth channel regions having an impurity concentration different from an impurity concentration of the third channel regions in a fourth region, wherein the first region and the second region are divided by a first line segment on the wafer, and the third and fourth regions are divided by a second line segment intersecting with the first line segment on the wafer.