Wafer Translator Metallization for High-Density Interdigitated Pads
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Solution Overview
Problem
Existing methods for testing semiconductor wafers often damage the conductive pads during electrical connection, and there is a need for a solution that allows for high-density placement of electrical components close to the integrated circuits without causing damage.
Innovation Solution
A wafer translator with a metallization pattern featuring high-density interdigitated contact pads and larger pads for external connections, where conductive material can be added or removed to reconfigure electrical pathways, allowing for flexible component placement and minimizing pad damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional probe card methods are used to contact conductive regions, then electrical testing can be performed, but the conductive pads are damaged during connection
Solution Approach 1:
The patent introduces a wafer translator as an intermediary device between the probe card and the wafer. The translator includes a substrate with contact pads on one side that interface with the wafer, and corresponding contact regions on the other side that interface with the probe card. This intermediary structure distributes and manages the mechanical and electrical stresses, preventing direct damage to the wafer's conductive pads while enabling reliable electrical testing.
2Productivity
If high-density component placement is required close to integrated circuits, then circuit functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The wafer translator substrate is divided into distinct functional regions: a first side with contact pads for wafer interfacing, a second side with contact regions for probe card interfacing, and intermediate conductive pathways. This segmentation allows independent optimization of each region - the contact pads can be positioned for high-density component placement while the internal metallization manages the complexity of electrical connections separately.
Solution Approach 2:
The patent utilizes the third dimension by creating a layered structure with conductive material deposited at different levels on the substrate. Multiple conductive layers are stacked and interconnected through vias or through-holes, allowing complex electrical pathways to be routed in three dimensions rather than confined to a single plane. This enables high-density component placement on the surface while managing sophisticated electrical connections through vertical interconnections.
Data Source
AI summary
A metallization pattern for a wafer translator provides a high density layout of interdigitated contact pads, suitable for component placement, along with larger contact pads suitable for connection to external equipment terminals. In another aspect, electrically conductive material may be added to, or removed from, the high density layout of interdigitated contact pads and larger contact pads to modify, or reconfigure, the electrical pathways of the wafer translator.