Multi-Planar Edge-Extended Wafer Translator Eliminates Probe Cards

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Solution Overview

Problem

Current semiconductor test equipment is complex and costly, making it inefficient for accurately routing electrical conductors to and from integrated circuits without compromising probe tip accuracy and signal integrity.

Innovation Solution

A multi-planar edge-extended wafer translator apparatus with a body having a central circular portion and bendable arms with connector tabs, allowing direct electrical connection between integrated circuit pads and pogo pins in a test system without a probe card, using electrically conductive pathways to match the pad layout and provide electrical continuity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If probe cards are used to contact integrated circuits on wafers, then electrical connection is achieved, but device complexity and cost increase

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidtest equipment complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the probe card from the test system by directly integrating the contact functionality into the wafer translator apparatus. The translator includes contact terminals that directly contact the integrated circuits on the wafer, eliminating the need for separate probe cards while maintaining electrical connection capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent combines the wafer translation function with the electrical contact function into a single integrated apparatus. The wafer translator simultaneously performs the mechanical function of positioning the wafer and the electrical function of contacting the integrated circuits, reducing overall system complexity

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If probe cards are used to route electrical conductors, then signal transmission is achieved, but manufacturing cost increases

Engineering Contradiction:
Improvesignal integrityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts the signal transmission function from the probe card and integrates it directly into the wafer translator. The translator includes conductive pathways that route electrical signals from the contact terminals to the test equipment interface, eliminating the need for expensive probe cards

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The wafer translator is designed as a multi-functional apparatus that simultaneously performs wafer positioning, electrical contact, and signal routing functions. This universal design replaces multiple separate components (positioning mechanism, probe card, connection interface) with a single integrated device, reducing manufacturing cost

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If multiple components are used in the test system, then functional requirements are met, but assembly error budget increases

Engineering Contradiction:
Improvetest system functionalityVSAvoiddimensional accuracy
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent merges multiple functional components into a single integrated wafer translator apparatus. By combining the positioning mechanism, contact terminals, and signal routing into one monolithic structure, the patent eliminates cumulative assembly errors that would arise from assembling multiple separate components

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The wafer translator is designed with modular contact terminals that can be configured to match different wafer layouts. The contact terminals are arranged in specific patterns that can be adapted to different integrated circuit configurations, maintaining functionality while reducing the need for multiple specialized components

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8704544B2Method and apparatus for multi-planar edge-extended wafer translator
Publication Date: 2014.04.22 TRANSLARITY INC
  • US8704544B2 patent drawing
  • US8704544B2 patent drawing
  • US8704544B2 patent drawing

AI summary

An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs.