Wafer Translator for Thinned Semiconductor Testing

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Solution Overview

Problem

Conventional semiconductor manufacturing processes face challenges in economically and mechanically practicing wafer level testing of integrated circuits after thinning and dicing, as existing methods are not feasible or practical.

Innovation Solution

A wafer translator with a patterned layer of wafer bonding thermoset plastic is removably attached to the wafer, providing mechanical support during thinning and dicing, and enabling electrical pathways for wafer level testing before separating the wafer and translator.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wafer level testing is performed after thinning and dicing using conventional methods, then testing can be conducted, but the process is not economically or mechanically feasible

Engineering Contradiction:
Improvetesting feasibilityVSAvoidmanufacturing feasibility
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The wafer translator is prepared in advance with a patterned layer of wafer bonding thermoset plastic before the wafer is attached. This preliminary preparation enables subsequent thinning and dicing operations while maintaining mechanical support and electrical connectivity, making post-dicing testing feasible

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The wafer translator acts as an intermediary device between the wafer and the testing equipment. It provides mechanical support during thinning and dicing while maintaining electrical pathways to the conductive regions, enabling testing after operations that would otherwise make testing impractical

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the wafer is thinned and diced before testing, then manufacturing steps are completed, but wafer level testing becomes impractical

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidtesting operability
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The wafer translator serves multiple functions: it provides mechanical support during thinning, maintains electrical connectivity during dicing, and enables testing after both operations are complete. This multi-functionality allows testing to be performed after manufacturing steps without requiring separate handling or support structures

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If additional handling steps are required for singulated die removal and packaging, then complete separation is achieved, but process complexity increases

Engineering Contradiction:
Improveseparation easeVSAvoidhandling steps
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The wafer bonding thermoset plastic layer is designed to be released after serving its purpose during thinning and dicing. The plastic layer can be discarded or recovered, allowing easy removal of singulated die from the wafer translator without requiring complex separation mechanisms or additional handling steps

Inventive Principle:
Principle #34Discarding and recovering

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient and practical wafer level testing of integrated circuits post-thinning and dicing, allowing for the removal and packaging of singulated die without the need for additional handling steps, thus improving the manufacturing process.

Implementation Method 1

A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair

Methodology Applied
Scientific EffectAdhesive bonding: Adhesive

Data Source

PatentUS8889526B2Apparatus for thinning, testing and singulating a semiconductor wafer
Publication Date: 2014.11.18 TRANSLARITY INC
  • US8889526B2 patent drawing
  • US8889526B2 patent drawing
  • US8889526B2 patent drawing

AI summary

A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.